White Electronic Designs
2Mx16 Flash MODULE, SMD 5962-97610
FEATURES
Access Times of 90, 120, 150ns
Packaging:
•
56 lead, Hermetic Ceramic, 0.520" CSOP
(Package 207).
Fits standard 56 SSOP footprint.
•
44 pin Ceramic SOJ (Package 102)**
•
44 lead Ceramic Flatpack (Package 208)**
Sector Architecture
•
32 equal size sectors of 64KBytes each
•
Any combination of sectors can be erased.
Also supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx16; User Configurable as 2 x 2Mx8
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
WF2M16-XXX5
PRELIMINARY*
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation.
RESET# pin resets internal state machine to the
read mode.
Ready/Busy (RY#/BY#) output for detection of
program or erase cycle completion.
Multiple Ground Pins for Low Noise Operation
* This product is under development, is not qualified or characterized and is subject to
change without notice.
** Package to be developed.
Note: For programming information refer to Flash Programming 16M5 Application Notes.
FIGURE 1 – PIN CONFIGURATIONS
WF2M16-XDAX5
56 CSOP
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
V
CC
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
TOP VIEW
CS1#
A12
A13
A14
A15
NC
CS2#
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY#
OE#
WE#
NC
I/O13
I/O5
I/O12
I/O4
V
CC
PIN DESCRIPTION
I/O
0-15
A
0-20
WE#
CS
1-2
#
OE#
VCC
VSS
RY/BY#
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
#RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
#RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
BLOCK DIAGRAM
I/O
0-7
RESET#
WE#
OE#
A
0-20
RY / B Y #
I/O
8-1
2M x 8
2M x 8
** Package to be developed.
CS
1#
CS
2#
NOTE:
1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
April 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Data Retention (Mil Temp)
Endurance — write/erase cycles
(Mil Temp)
WF2M16-XXX5
PRELIMINARY
CAPACITANCE
(T
A
= +25°C)
Unit
V
W
°C
mA
years
cycles
Symbol
V
T
P
T
T
STG
I
OS
Ratings
-2.0 to +7.0
8
-65 to +125
100
20
100,000 min.
Parameter
OE# capacitance
WE# capacitance
CS# capacitance
Data I/O capacitance
Address input capacitance
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Conditions
Max Unit
V
IN
= 0V, f = 1.0 MHz 25
pF
V
IN
= 0V, f = 1.0 MHz 25
pF
V
IN
= 0V, f = 1.0 MHz 15
pF
V
I/O
= 0V, f = 1.0 MHz 15
pF
V
IN
= 0V, f = 1.0 MHz 25
pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol
V
CC
V
SS
V
IH
V
IL
T
A
T
A
Min
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
–
–
–
–
Max
5.5
0
V
CC
+ 0.5
+0.8
+125°C
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS - CMOS COMPATIBLE
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IL
, OE# = V
IH
V
CC
= 5.5, CS# = V
IH
,
f = 5MHz, RESET# = V
CC
± 0.3V
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
Min
Max
10
10
80
120
4.0
0.45
0.85xV
CC
3.2
4.2
Unit
µA
µA
mA
mA
mA
V
V
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
April 2004
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width
NOTES:
1. Typical value for t
WHWH1
is 7µs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
WF2M16-XXX5
PRELIMINARY
AC Characteristics – Write/Erase/Program Operations - WE# Controlled
Symbol
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
Min
90
0
45
0
45
0
45
20
-90
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
ns
Unit
300
15
0
50
44
256
t
OEH
t
RP
10
500
10
500
0
50
300
15
0
50
44
256
10
500
300
15
44
256
AC CHARACTERISTICS – READ-ONLY OPERATIONS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE# Change,
whichever is First
RESET# Low to Read Mode (1)
1. Guaranteed by design, not tested.
Symbol
Min
T
AVAV
T
AVQV
T
ELQV
T
GLQV
T
EHQZ
T
GHQZ
T
AXQX
T
RC
T
ACC
T
CE
T
OE
T
DF
T
DF
T
OH
T
READY
0
90
-90
Max
90
90
40
20
20
0
20
-120
Min
120
120
120
50
30
30
0
20
-150
Max
Min
150
150
150
55
35
35
Unit
Max
ns
ns
ns
ns
ns
ns
ns
20
µs
April 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for t
WHWH1
is 7µs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
t
OEH
10
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
0
44
256
10
WF2M16-XXX5
PRELIMINARY
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
Symbol
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
Min
90
0
45
0
45
0
45
20
300
15
0
44
256
10
-90
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
300
15
0
300
15
44
256
µs
sec
µs
sec
sec
ns
FIGURE 2 – AC TEST CIRCUIT
AC TEST CONDITIONS
I
OL
Current Source
D.U.T.
C
EFF
= 50 pf
V
Z
1.5V
(Bipolar Supply)
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ½.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.ATE
tester includes jig capacitance.
FIGURE 3 – RESET TIMING DIAGRAM
RESET#
t
RP
t
Ready
April 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF2M16-XXX5
PRELIMINARY
FIGURE 3 – AC WAVEFORMS FOR READ OPERATIONS
t
DF
t
OH
Addresses Stable
t
RC
t
OE
t
ACC
t
CE
FDx
FOE#
FWE#
April 2004
Rev. 5
FCS1#/FCS2#
Addresses
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Outputs
FDx
High Z
Output Valid
High Z
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