PO74G240A
OCTAL 3-STATE BUS INVERTERS
74 Series GHz Logic
10/22/07
FEATURES:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 300MHz with 15pf load
. Operating frequency up to 100MHz with 50pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 20pin TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO74G240A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This Octal bus inverter gate is designed for 1.65-V to
3.6-V V
CC
operation.
The
PO74G240A
features independent line driver swith
3-state outputs. Each output is disabled when the
associated output- enable(OE) input is high.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Logic Block Diagram
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1OE
1
1A1
2
18
1Y1
1A2
4
16
1Y2
1A3
6
14
1Y3
1A4
8
12
1Y4
2OE
19
Pin Description
INPUTS
OE
L
L
H
A
H
L
X
OUTPUT
Y
L
H
Z
2A1
11
9
2Y1
2A2
13
7
2Y2
2A3
15
5
2Y3
2A4
17
3
2Y4
1
Copyright
© Potato Semiconductor Corporation
PO74G240A
OCTAL 3-STATE BUS INVERTERS
74 Series GHz Logic
10/22/07
Maximum Ratings
Description
Storage Temperature
Operation Temperature
Operation Voltage
Input Voltage
Output Voltage
Max
-65 to 150
-40 to 85
-0.5 to +4.6
-0.5 to +5.5
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
Output High voltage
Output Low voltage
Input High voltage
Input Low voltage
Input High current
Input Low current
Clamp diode voltage
Test Conditions
Vcc=3V Vin=V
IH
or V
IL
, I
OH
= -12mA
Vcc=3V Vin=V
IH
or V
IL
, I
OH
=12mA
Guaranteed Logic HIGH Level (Input Pin)
Guaranteed Logic LOW Level (Input Pin)
Vcc = 3.6V and Vin = 5.5V
Vcc = 3.6V and Vin = 0V
Vcc = Min. And
I
IN
= -18mA
Min
Typ
Max
Unit
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
V
IK
Notes:
1.
2.
3.
4.
5.
2.4
-
2
-0.5
-
-
-
3
0.3
-
-
-
-
-0.7
-
0.5
5.5
0.8
1
-1
-1.2
V
V
V
V
uA
uA
V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25
°C
ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright
© Potato Semiconductor Corporation
PO74G240A
OCTAL 3-STATE BUS INVERTERS
74 Series GHz Logic
10/22/07
Power Supply Characteristics
Symbol
Description
Quiescent Power Supply Current
Power Supply Current per Input High
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Vcc=Max, Vin= Vcc-0.6V
Min
Typ
Max
Unit
Icc
Q
∆Icc
Notes:
1.
2.
3.
4.
5.
-
-
0.1
50
30
300
uA
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Description
Input Capacitance
Output Capacitance
Test Conditions
Vin = 0V
Vout = 0V
Typ
Unit
Cin
Cout
Notes:
4
6
pF
pF
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
Propagation Delay A to Y
Propagation Delay A to Y
Output Enable Time
Output Disable Time
Rise/Fall Time
Input Frequency
Input Frequency
Input Frequency
Input Frequency
Test Conditions (1)
CL = 15pF
CL = 15pF
CL = 15pF
CL = 15pF
0.8V – 2.0V
CL = 50 pF
CL =15pF
CL = 5pF
CL = 2pF
M ax
Unit
t
PLH
t
PHL
t
PZH or
t
PZL
t
PHZ or
t
PLZ
tr/tf
fmax
fmax
fmax
fmax
Notes:
1.5
1.5
2.5
2.5
0.8
100
300
750
1125
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright
© Potato Semiconductor Corporation
PO74G240A
OCTAL 3-STATE BUS INVERTERS
74 Series GHz Logic
10/22/07
Test Waveforms
Intput
t
PLH
t
PHL
V
OH
2.0V
1.5V
0.8V
V
OL
Intput
t
PLH
t
PHL
V
OH
1.5V
V
OL
Output
t
R
t
F
Output
Intput
Intput
Output 1
Package1
Output
Output 2
Package2
Output
Test Circuit
500
Ω
50
Ω
50pF
to
2pF
50
Ω
500
Ω
4
Copyright
© Potato Semiconductor Corporation
PO74G240A
OCTAL 3-STATE BUS INVERTERS
74 Series GHz Logic
10/22/07
Packaging Mechanical Drawing: 20 pin TSSOP
20
.169
.177
4.3
4.5
.018
.030
0.45
0.75
.238
.269
6.1
6.7
1
.252
.260
6.4
6.6
.047
1.20
Max
.004
0.09
.008
0.20
SEATING
PLANE
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
0.05
.006
0.15
X.XX
DENOTES DIMENSIONS
X.XX
IN MILLIMETERS
5
Copyright
© Potato Semiconductor Corporation
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