M
O
S
YS
1+ '
9PXVE 0S[ 0EXIRG] ,MKL 4IVJSVQERGI
/\ 7+6%1
4VIPMQMREV] -RJSVQEXMSR
®
Features
High bandwidth 100MHz-200MHz operation
Reduced Latency - 13ns access, 25ns cycle
Improved critical timing parameter limits
2/4 Internal Banks for hiding Row Precharge
Full SGRAM protocol
Independent byte operation via DQM[3:0]
Burst length - 1,2,4,8 and full page
Burst Type: Linear, Wrap
Capacity: 16Mb
Organization: 512Kx32
Refresh Interval 15.6uSec
CBR Refresh.
Self Refresh
LVTTL and SSTL compatible Interface
Supply voltages - 3.3 V
±
0.3V
Package - 100-pin QFP
DQ3
VddQ
DQ4
DQ5
VssQ
DQ6
DQ7
VddQ
DQ16
DQ17
VssQ
DQ18
DQ19
VddQ
Vdd
Vss
DQ20
DQ21
VssQ
DQ22
DQ23
VddQ
DQM0
DQM2
WE#
CAS#
RAS#
CS#
BA0
A10/BA1
Overview
The M
O
S
YS
16MbSGRAM is a second generation, synchronous memory, designed for for
graphics, multimedia, networking and other applications. It offers short Precharge (t
RP
), faster
Access Latency (t
RC
, t
RAS
, t
RCD
and CL=2) and higher clock rates. In addition to the SGRAM
command set, the M
O
S
YS
SGRAM implements an eight column Block Write function and a
Masked Write (Write Per Bit) function to accommodate graphics applications.
Options
MoSys SGRAM supports the following device options
Option
200MHz - 5.0ns Cycle Time
166MHz - 6.0ns Cycle Time
150MHz - 6.6ns Cycle Time
133MHz - 7.5ns Cycle Time
125MHz - 8.0ns Cycle Time
Marking
-5
-6
-6R6
-7R5
-8
Part Number Designation
Example:
MG802C512QR -7R5
Device Designation:
MG8
, Series:
02C
Organization:
512Kx32
Package Type:
Q
=PQFP,
L
=LQFP
Pinout:
R
=
Reverse (Mirror Image)
Speed:
– 7 R 5
=133MHz
DS08, Rev 1.3 - 05/04/98
Preliminary Information
© 1998MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
A0
A1
A2
A3
Vdd
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
A4
A5
A6
A7
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQ2
VssQ
DQ1
DQ0
Vdd
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
DQ31
DQ30
VssQ
DQ29
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 Pin QFP
20 mm x 14 mm body
0.65 mm nominal pin pitch
DQ28
VddQ
DQ27
DQ26
VssQ
DQ25
DQ24
VddQ
DQ15
DQ14
VssQ
DQ13
DQ12
VddQ
Vss
Vdd
DQ11
DQ10
VssQ
DQ9
DQ8
VddQ
NC/VREF
DQM3
DQM1
CLK
CKE
DSF
NC
A8/AP
Page 1
M
O
S
YS
1+ '
9PXVE 0S[ 0EXIRG] ,MKL 4IVJSVQERGI
/\ 7+6%1
4VIPMQMREV] -RJSVQEXMSR
®
Functional Description
Pin Description
Pin
Name
CLK
CS#
CKE
Pin Number
55
28
54
Pin
Total
1
1
1
I/O
I
I
I
Description
A10/BA1
A[8:0]
RAS#
CAS#
WE#
DSF
DQM[3:0]
30
51-47, 34-31
27
26
25
53
57, 24, 56, 23
1
10
1
1
1
1
4
I
I
I
I
I
I
DQ[31:0]
BA/BA0
84, 83, 81, 80,
78, 77, 75, 74,
1, 20, 18, 17,
13, 12, 10, 9,
72, 71, 69, 68,
64, 63, 61, 60,
7, 6, 4, 3, 1,
100, 98, 97
29
32
I/O
System Clock:
All inputs are sampled on positive edge.
Chip select:
Disables or enables the device operation by
masking or enabling all inputs except CLK, CKE and DQM.
Clock Enable:
CKE controls the Power Down Mode in
M
O
S
YS
SGRAM. When in Power Down Mode all input and
output buffers are de-activated.
Bank Select:
Banks Select in 4 Bank mode
Address Inputs:
Row & Column address are multiplexed on
the same pins.
Row Address Strobe:
Latches Row address on the positive
edge of clock with RAS# low. Enables Row access.
Column Address Strobe:
Latches Column Address on the
positive edge of clock. Enables column access.
Write Enable:
Enables write operation.
DSF:
Enables the Write Per Bit and Block Write function.
This pin has an internal pull-down resistor.
Data Input/Output Mask:
Write data byte mask, Read
output byte enables. Read latency is two cycle from DQM
and zero cycle for write. The DQM masking occurs two
cycles later in the Read operation and in the same cycle
during Write operation. DQM is synchronous to the clock,
thus the masking occurs for the whole clock.
Data Input/Output:
Bidirectional data bus.
Bank Address 0:
Bank Address defines to which Bank the
Activate, Read, Write or Precharge Command is issued.
th
BA0 is also used to program the 10 bit of the Mode
Register.
Signal description for 512Kx32 MoSys SGRAM
Input
I
Parameter
2 Bank
4Bank
Bank Address
BA (A9)
BA0, BA1
Row Address
A[8:0], A10
A[8:0]
Column Address
A[7:0]
A[7:0]
Auto Precharge
A8
A8
Page Size
256x32
256x32
Bank, Row and Column Address mapping
DS08, Rev 1.3 - 05/04/98
Preliminary Information
Page 2
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
M
O
S
YS
1+ '
9PXVE 0S[ 0EXIRG] ,MKL 4IVJSVQERGI
/\ 7+6%1
4VIPMQMREV] -RJSVQEXMSR
®
CONTROL REGISTERS
M
O
S
YS
SGRAM incorporates four programmable registers, the Mode Select Register (MSR),
Special Mode Register (SMR), Color Register (CR) and the Mask Register (MR). This section
describes the use of these registers. In describing the functionality, the following terms are used.
WO
R
Write Only.
A register bit with this attribute is Write Only.
Reserved.
A register bit with this attribute is Reserved.
Mode Register (MSR)
M
O
S
YS
SGRAM’s mode register is accessed through the Mode Register Write Command (op
code ‘00000’). Mode Register is used to load the value of CAS Latency and Burst Length of
M
O
S
YS
SGRAM.
Bit
8:7
Default
00
Attribute
WO
Description
Reserved:
00
01
10
11
6:4
011
WO
Standard operation (2 Banks)
Reserved (for M
O
S
YS
Use only)
Standard operation (4 Banks)
Reserved (for M
O
S
YS
Use only)
CAS Latency:
000
Reserved
001
1
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Burst Type:
0=Linear Burst Mode, 1=Wrap Mode
Burst Length:
BT=0
BT=1
000
1
1
001
2
2
010
4
4
011
8
8
100
Reserved
Reserved
101
Reserved
Reserved
110
Reserved
Reserved
111
Full Page
Reserved
Description of Mode Register
3
2:0
0
010
WO
WO
DS08, Rev 1.3 - 05/04/98
Preliminary Information
Page 3
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
M
O
S
YS
1+ '
9PXVE 0S[ 0EXIRG] ,MKL 4IVJSVQERGI
/\ 7+6%1
4VIPMQMREV] -RJSVQEXMSR
®
Special Mode Register (SMR)
M
O
S
YS
SGRAM’s Special Mode Register is accessed through the Mode Register Read/Write
Command (op code ‘00001’). Special Mode Register is used to load data into the Color Register
or the Mask register. During the execution of the Special Mode Register Command Bits A[6:5]
are used to determine if a new value is to be loaded into the Color and Mask Registers.
Bit
BA0, A[8:7]
A[6]
A[5]
A[4:0]
Default
000
0
0
0000
Attribute
WO
Description
Reserved:
For Standard operation these bits should always be
“000”.
WO
Color Register:
0=Leave data unchanged for Color Register,
1=Load new data into Color Register.
WO
Mask Register:
0=Leave data unchanged for Mask Register,
1=Load new data into Mask Register.
WO
Reserved:
For Standard operation these bits should always
be “0000”.
Description of Special Mode Register
Color Register (CR)
Data is loaded into the Color Register through the Special Mode Register Write Command. During
the execution of the Special Mode Register Command, bit A[6] is used to determine if a new
value is to be loaded into the Mask Registers. If A[6] =1 during the Special Mode Register
Command then the value on DQ[31:0] is loaded into the Color Register. The Color Register
supplies data for the Block Write Command.
Bit
31:0
Default
00000000h
Attribute
WO
Description
Color Register Data:
Data from these bits is used for Block
Write Command.
Description of Color Register
Mask Register (MR)
Data is loaded into the Mask Register through the Special Mode Register Write Command.
During the execution of the Special Mode Register Command, bit A[5] is used to determine if a
new value is to be loaded into the Mask Registers. If A[5] =1 during the Special Mode Register
Command then the value on DQ[31:0] is loaded into the Mask Register. The Mask Register is
used for Mask Per Bit functionality during the Masked Write of Masked Block Write Command.
Mask Per Bit is used in conjunction with the DQM[3:0] to determine the mask for each bit.
Bit
31:0
Default
00000000h
Attribute
WO
Description
Mask Register Data:
Data from these bits is used for Masked
Write and Block Write Command.
Description of Mask Register
DS08, Rev 1.3 - 05/04/98
Preliminary Information
Page 4
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
M
O
S
YS
1+ '
9PXVE 0S[ 0EXIRG] ,MKL 4IVJSVQERGI
/\ 7+6%1
4VIPMQMREV] -RJSVQEXMSR
®
DEVICE OPERATION
This section provides a description of M
O
S
YS
SGRAM device.
Device Function
The following command table lists all supported M
O
S
YS
SGRAM commands. All fixed length burst
(non full page burst length) operations can be self terminated, terminated by BST, interrupted by
another Read or Write operation or by a Precharge operation to the same Bank. For Auto
Precharge Read or Write, the operation cannot be interrupted and has to self-terminate after the
programmed burst length. Auto Precharge has no effect for a full page burst length operation. To
provide backward compatibility with SDRAM command set, the M
O
S
YS
SGRAM incorporates an
internal pull-down resistor for the DSF pin.
Mode Register Write
The Mode Register stores data for controlling various functions of M
O
S
YS
SGRAM. Through the
mode register the CAS Latency, Burst Type, Burst Length and the PLL enable mode can be
programmed for the device. The default value of the Mode Register is defined as CAS Latency of
3, Burst Type of linear and Burst Length of 4. The Mode Register is written to by driving CS#,
RAS#, CAS#, WE# and DSF low.
Special Mode Register Write
The Special Mode Register controls the data written to Color or Mask Register of M
O
S
YS
SGRAM. During the Special Mode Register Command A[6:5] are used to indicate to the M
O
S
YS
SGRAM whether a new data pattern is to be written to Color or Mask Registers. The Special
Mode Register is written to by driving CS#, RAS#, CAS#, WE# and DSF high.
Bank Activate
The Bank Activate Command selects a Row in a Bank. Bank is activated by driving CS# low,
RAS# low, CAS# high, WE# high and DSF low with the correct Bank and Row specified on BA
and A[8:0]. The Read/Write Command can follow the Activate Command after the t
RCD
timing has
been met. Every Bank Activate Command must satisfy the minimum t
RAS
before a Precharge
Command can be issued to that Bank.
Activate with WPB
The Bank Activate with WPB Command selects a random Row in an idle Bank. Bank is activated
by driving CS# low, RAS# low, CAS# high, WE# high and DSF high with the correct Bank and
Row specified on A[10/9:0]. The Write or Block Write Command can follow the Activate
Command after the t
RCD
timing has been met. A Write Command to the selected Bank will be
masked according to the contents of the Mask Register and DQM[3:0]. A Block Write Command
following the Activate with WPB Command will be masked according to the contents of the Mask
Register, DQM[3:0] and the Column/Byte Mask information on the DQ[31:0] pins.
Read
The Read Command is used to access data from an active Row and Bank within the device. The
Read Command is issued by driving CS# low, RAS# high, CAS# low, WE# high and A8 low (no
DS08, Rev 1.3 - 05/04/98
Preliminary Information
Page 5
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
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