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-1-
K4T51043QI
K4T51083QI
K4T51163QI
datasheet
History
- First Spec. Release
- Corrected Typo.
Draft Date
Mar. 2010
Jul. 2011
Rev. 1.1
DDR2 SDRAM
Revision History
Revision No.
1.0
1.1
Remark
-
-
Editor
S.H.Kim
J.Y.Lee
-2-
K4T51043QI
K4T51083QI
K4T51163QI
datasheet
Rev. 1.1
DDR2 SDRAM
Table Of Contents
512Mb I-die DDR2 SDRAM
1. Ordering Information ..................................................................................................................................................... 4
6. Absolute Maximum Ratings .......................................................................................................................................... 12
7. AC & DC Operating Conditions..................................................................................................................................... 12
7.1 Recommended DC operating Conditions (SSTL_1.8)............................................................................................. 12
7.2 Operating Temperature Condition ........................................................................................................................... 13
7.3 Input DC Logic Level ............................................................................................................................................... 13
7.4 Input AC Logic Level ............................................................................................................................................... 13
7.5 AC Input Test Conditions......................................................................................................................................... 13
7.6 Differential input AC logic Level............................................................................................................................... 14
7.7 Differential AC output parameters ........................................................................................................................... 14
8. ODT DC electrical characteristics ................................................................................................................................. 14
10. IDD Specification Parameters and Test Conditions .................................................................................................... 16
13. Electrical Characteristics & AC Timing for DDR2-1066/800/667 ................................................................................ 20
13.1 Refresh Parameters by Device Density................................................................................................................. 20
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 20
13.3 Timing Parameters by Speed Grade ..................................................................................................................... 21
14. General notes, which may apply for all AC parameters .............................................................................................. 23
15. Specific Notes for dedicated AC parameters .............................................................................................................. 25
-3-
K4T51043QI
K4T51083QI
K4T51163QI
datasheet
DDR2-1066 7-7-7
-
-
DDR2-800 5-5-5
K4T51043QI-HC(L)E7
K4T51083QI-HC(L)E7
K4T51163QI-HC(L)E7
DDR2-800 6-6-6
K4T51043QI-HC(L)F7
K4T51083QI-HC(L)F7
K4T51163QI-HC(L)F7
Rev. 1.1
DDR2 SDRAM
DDR2-667 5-5-5
K4T51043QI-HC(L)E6
K4T51083QI-HC(L)E6
K4T51163QI-HC(L)E6
Package
60 FBGA
60 FBGA
84 FBGA
1. Ordering Information
Org.
128Mx4
64Mx8
32Mx16
K4T51163QI-HC(L)F8
NOTE
:
1. Speed bin is in order of CL-tRCD-tRP
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an
optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-50ohm ODT
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
The 512Mb DDR2 SDRAM is organized as a 8Mbit x16 I/Os,16Mbit x8 I/Os,
32Mbit x4 I/Os 4banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1066Mb/sec/pin (DDR2-
1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM fea-
tures such as posted CAS with additive latency, write latency = read latency
-1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. For example, 512Mb(x8)
device receive 14/10/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V power supply
and 1.8V ± 0.1V V
DDQ
.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball
FBGAs(x16)
NOTE
:
1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia-
gram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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