HI-8599
June 2012
ARINC 429
Transmitter with Line Driver and Dual Receivers
FEATURES
!
ARINC specification 429 compliant
!
Direct receiver and transmitter interface to
ARINC bus in a single device
!
16-Bit parallel data bus
!
Timing control 10 times the data rate
!
Selectable data clocks
!
Receiver error rejection per ARINC
specification 429
!
Automatic transmitter data timing
!
Self test mode
!
Parity functions
!
Low power
!
Industrial & full military temperature ranges
GENERAL DESCRIPTION
The HI-8599 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. This device provides
two receivers, an independent transmitter and line driver
capability in a single package. The receiver input circuitry
and logic are designed to meet the ARINC 429
specifications for loading, level detection, timing, and
protocol. The transmitter section provides the ARINC 429
communication protocol and the line driver circuits
provide the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces
with CMOS and TTL.
The HI-8599 provides the option to bypass most of the
internal output resistance so that external series
resistance may be added for lighting protection and still
match the 75 ohm characteristic impedance of the ARINC
bus.
Each independent receiver monitors the data stream with
a sampling rate 10 times the data rate. The sampling rate
is software selectable at either 1MHz or 125KHz. The
results of a parity check are available as the 32nd ARINC
bit. The HI-8599 examines the null and data timings and
will reject erroneous patterns. For example, with a 125
KHz clock selection, the data frequency must be between
10.4 KHz and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of
the transmitter is software selectable by dividing the
master clock, CLK, by either 10 or 80. The master clock is
used to set the timing of the ARINC transmission within the
required resolution.
The HI-8599 is nearly identical to the HI-8589 but has a
TEST input pin not found in the HI-8589.
PIN CONFIGURATION
(Top View)
- 429DI2(A)
- 429DI1(B)
- 429DI1(A)
- VCC
- TEST
- MR
- TXCLK
- CLK
- N/C
- N/C
- CWSTR
429DI2(B) - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
44
43
42
41
40
39
38
37
36
35
34
HI-8599PQI
&
HI-8599PQT
33 - ENTX
32 - N/C
31 - V+
30 - TXB(OUT)
29 - TXA(OUT)
28 - V-
27 - GND
26 - TX/R
25 - PL2
24 - PL1
23 - BD00
APPLICATIONS
!
Avionics data communication
!
Serial to parallel conversion
!
Parallel to serial conversion
(DS8599 Rev.C)
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 13 for additional pin configurations)
HOLT INTEGRATED CIRCUITS
www.holtic.com
BD10 - 12
BD09 - 13
BD08 - 14
BD07 - 15
BD06 - 16
GND - 17
BD05 - 18
BD04 - 19
BD03 - 20
BD02 - 21
BD01 - 22
06/12
HI-8599
PIN DESCRIPTION
SIGNAL
V
CC
V+
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
TX/R
PL1
PL2
TXA(OUT)
TXB(OUT)
ENTX
CWSTR
CLK
TX CLK
MR
TEST
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
+5V ±5%
+9.5V to +10.5V
-9.5V to -10.5V
DESCRIPTION
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
Disable Transmitter output if high (pull-down)
HOLT INTEGRATED CIRCUITS
2
HI-8599
FUNCTIONAL DESCRIPTION (cont.)
CONTROL WORD REGISTER
The HI-8599 contains 10 data flip flops whose D inputs are
connected to the data bus and clocks connected to CWSTR.
Each flip flop provides options to the user as follows:
DATA
BUS
PIN
BDO5
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
FUNCTION CONTROL
DESCRIPTION
If enabled, the transmitter’s digital
outputs are internally connected
to the receiver logic inputs
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
If enabled, ARINC bits 9 and
10 must match the next two
Control word bits
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
CLK is divided either by 10 or
80 to obtain XMTR data clock
CLK is divided either by 10 or
80 to obtain RCVR data clock
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
SELF TEST
0 = ENABLE
BDO6
RECEIVER 1
DECODER
1 = ENABLE
BYTE 2
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO7
-
-
BDO8
-
-
THE RECEIVERS
ARINC BUS INTERFACE
BDO9
RECEIVER 2
DECODER
1 = ENABLE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
BD10
-
-
BD11
-
-
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BD12
INVERT
XMTR
PARITY
XMTR DATA
CLK SELECT
RCVR DTA
CLK SELECT
1 = ENABLE
The HI-8599 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BD13
0 = ÷10
1 = ÷80
0 = ÷10
1 = ÷80
BD14
v
cc
429DI1 (A)
OR
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
429DI2 (A)
GND
NULL
v
cc
429DI1 (B)
OR
ZEROES
429DI2 (B)
GND
FIGURE 1.
ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HI-8599
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing each receiver’s logic.
BIT TIMING
ARINC 429 specifies the following timing for received data:
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 - 41.7 µsec
bit rate is checked. With exactly 1 MHz input clock frequency,
the acceptable data bit rates are as follows:
HIGH SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 enables the next reception.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver remains low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by first acti-
vating EN with SEL, the byte selector, low to retrieve the first byte
and then activating EN with SEL high to retrieve the second byte.
EN1 retrieves data from receiver 1 and EN2 retrieves data from re-
ceiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
The HI-8581 and HI-8589 accepts signals meeting these specifi-
cations and rejects signals outside these tolerances using the
method described here:
1. The timing logic requires an accurate 1.0 MHz clock
source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. To qualify data bits, One or Zero in the upper
bits of the sampling shift register must be followed by Null in
the lower bits within the data bit time. A word gap Null re-
quires three consecutive Nulls in both the upper and lower
bits of the sampling shift register. This guarantees the mini-
mum pulse width.
3. Each data bit must follow its predecessor by not less than
8 samples and not more than 12 samples. In this manner the
TO PINS
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
32 TO 16 DRIVER
CONTROL
BIT BD14
CLOCK
OPTION
CLOCK
CLK
/
LATCH
ENABLE
CONTROL
BITS 9 & 10
32 BIT LATCH
BIT
COUNTER
AND
END OF
SEQUENCE
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT CLOCK
EOS
EOS
ONES
WORD GAP
WORD GAP
TIMER
BIT CLOCK
SHIFT REGISTER
START
END
NULL
SHIFT REGISTER
SEQUENCE
CONTROL
ZEROS
SHIFT REGISTER
ERROR
ERROR
DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HI-8599
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The Receiver Parity Check Enable bit (Control Register bit 4,
CR4) controls how the 32nd bit of the received ARINC word is
interpreted by the HI-3585 receiver.
When CR4 is set to a “0”
, the 32nd bit is treated as data and
transferred as received from the ARINC bus to the receive FIFO.
When CR4 is set to a “1”
, the 32nd bit is treated as a parity
error bit.
Odd Parity Received
The receiver expects the 32nd bit of the received word to
indicate odd parity. If this is the case, the parity bit is reset to
indicate correct parity was received and resulting word is
written to the receive FIFO.
Even Parity Received
If the received word is even parity, the receiver sets the 32nd
bit to a “1”, indicating a parity error. The resulting word is then
written to the receive FIFO.
Therefore, when CR4 is set to “1”, the 32nd bit retrieved from the
receiver FIFO will always be “0” when valid (odd parity) ARINC 429
words are received.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO positions
are incremented with the top register loading into the data
transmission shift register. Within 2.5 data clocks the first data bit
appears at either TXA(OUT) or TXB(OUT). The 31 bits in the data
transmission shift register are presented sequentially to the outputs
in the ARINC 429 format with the following timing:
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
The word counter detects when all loaded positions are transmitted
and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs. Taking
TEST high forces TXA(OUT) and TXB(OUT) into the null state
regardless of the state of Bd05 control word bit.
CR4
0
1
ARINC BUS
32nd bit
data
parity bit
FIFO
32nd bit
data
Error Bit:
0 = odd parity
1= odd parity error (even parity)
SYSTEM OPERATION
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1.
2.
3.
4.
5.
The received data may be overwritten if not retrieved within
one ARINC word cycle.
The FIFO can store 8 words maximum and ignores attempts to
load addition data if full.
Byte 1 of the transmitter data must be loaded first.
Either byte of the received data may be retrieved first. Both
bytes must be retrieved to clear the data ready flag.
After ENTX, transmission enable, goes high it cannot go low
until TX/R, transmitter ready flag, goes high. Otherwise, one
ARINC word is lost during transmission.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words, each
31 bits long, may be loaded. If TX/R is low, then only the available
positions may be loaded. If all 8 positions are full, the FIFO ignores
further attempts to load data.
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