TSI381-66IL datasheet, PDF - EEWORLD Datasheet

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TSI381-66IL: DescriptionPCI Bus Controller, CMOS, PBGA144, 13 X 13 MM, GREEN, PLASTIC, BGA-144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size116KB，2 Pages; ManufacturerTundra Semiconductor Corp

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TSI381-66IL Overview

PCI Bus Controller, CMOS, PBGA144, 13 X 13 MM, GREEN, PLASTIC, BGA-144

TSI381-66IL Parametric

Parameter Name	Attribute value
package instruction	13 X 13 MM, GREEN, PLASTIC, BGA-144
Reach Compliance Code	unknown
Address bus width	32
Bus compatibility	PCI
maximum clock frequency	66 MHz
Drive interface standards	IEEE 1149.6; IEEE 1149.1
External data bus width	32
JESD-30 code	S-PBGA-B144
length	13 mm
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.8 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI
Base Number Matches	1

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Tsi381

™

PCI Express to PCI Bridge

Features

General

• PCI Express to PCI bridge

• Transparent, Non-transparent and

Opaque modes

• Efficient queuing and buffering for low

latency and high throughput

• Compliant with the following

specifications:

– PCI Express Base 1.1

– PCI Express PCI/PCI-X Bridge 1.0

– PCI-to-PCI Bridge Architecture 1.2

– PCI Local Bus 3.0

– PCI Bus Power Mgt. Interface 1.2

PCI Express

The Tundra Semiconductor Tsi381 is a high-performance bus bridge that

connects the PCI Express protocol to the PCI bus standard. The Tsi381’s

PCIe Interface supports a x1 lane PCIe configuration, which enables the

bridge to offer exceptional throughput performance of up to 2.5 Gbps per

transmit and receive direction.

The device’s PCI Interface can operate up to 66 MHz. This interface offers

designers extensive flexibility by supporting three types of addressing modes:

transparent, opaque, and non-transparent.

Block Diagram

Clocking/

Reset

PCIe Interface (x1)

EEPROM

Controller

x1 lane PCIe Interface

Advanced error reporting capability

End-to-end CRC check and generation

Up to four outstanding memory reads

ASPM L0 link state power management

Legacy interrupt signaling and MSI

interrupts

• Hot Plug support

PCI

•

Interrupt

Handling

Posted

Writer

Buffer

Non-

Posted

Buffer

Posted

Queue

Non-

Posted

Queue

Upstream

Mux Logic

Power

Mgmt

Error

Handling

Mux Logic

GPIO

Downstream

Posted

Writer

Buffer

Non-

Posted

Buffer

Posted

Queue

Non-

Posted

Queue

Config

Registers

32/64-bit addressing and 32-bit data

Operates at 25, 33, 50, and 66 MHz

Up to eight outstanding memory reads

3.3V PCI I/Os, 5V tolerant

Four external PCI masters supported

through internal arbiter

• MSI generation and handling using

interrupt and GPIO signals

•

PCI

Arbiter

PCI Interface

JTAG

80E2000_BK001_03 (Tsi381)

Simplest, Low-Risk Design

The Tsi381 simplifies board design by using only two power supplies with no

power sequencing constraints. Its package is designed to simplify board

layout for high reliability and signal integrity. A comprehensive suite of

design support resources are also available to aid designers.

Pin compatibility with the PLX PEX8111 and PEX8112 make it easy for

designers to migrate current designs to the Tsi381, and thereby bring them

to market quickly and with low risk.

TSI381-66IL Related Products

	TSI381-66IL	TSI381-66ILV
Description	PCI Bus Controller, CMOS, PBGA144, 13 X 13 MM, GREEN, PLASTIC, BGA-144	PCI Bus Controller, CMOS, PBGA144, 13 X 13 MM, GREEN, PLASTIC, BGA-144
package instruction	13 X 13 MM, GREEN, PLASTIC, BGA-144	13 X 13 MM, GREEN, PLASTIC, BGA-144
Reach Compliance Code	unknown	unknown
Address bus width	32	32
Bus compatibility	PCI	PCI
maximum clock frequency	66 MHz	66 MHz
Drive interface standards	IEEE 1149.6; IEEE 1149.1	IEEE 1149.6; IEEE 1149.1
External data bus width	32	32
JESD-30 code	S-PBGA-B144	S-PBGA-B144
length	13 mm	13 mm
Number of terminals	144	144
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.8 mm	1.8 mm
Maximum supply voltage	1.26 V	1.26 V
Minimum supply voltage	1.14 V	1.14 V
Nominal supply voltage	1.2 V	1.2 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
width	13 mm	13 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI
Base Number Matches	1	1

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