— Function compatible with ATM Forum af-phy-0136.000
— Asynchronous/synchronous FIFO using RAM
— Up to 256 PHY ports supported
— 8/16/32 bit interfaces supported
— Direct and polled status
— Simple system side FIFO interface
— Flow control and polling integrated
top_ing_slave
RxClk
RxData
RxEnb_n
RxClav
RxPrty
RxSoc
RxAddr
fifo_16 / fifo_8
tx_utopia3_slave
reset_n
wr_data
wr_flag
wr_enb
wr_clk
Targeted Devices:
— ProASIC
®
3 Family
fifo_16 / fifo_8
rd_data
rd_enb
rd_flag
rx_utopia3_slave
— Axcelerator
®
Family
— ProASIC
PLUS®
Family
Core Deliverables:
— Netlist Version
> Compiled RTL simulation model, compliant with the Actel
Libero
®
environment
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
Block Diagram
> VHDL Source Code
— All
> User Guide
> Test Bench
UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 3 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA Level 3 standard defines a full duplex interface with a Master/Slave format.
The Slave or LINK layer device responds to the requests from the PHY or Master
device. The Master performs PHY arbitration and initiates data transfers to and from
the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in
width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps.
Synthesis and Simulation Support:
— Synthesis: Synplicity
®
— Simulation: ModelSim
®
— Other tools supported upon request
Verification:
— Test Bench
— Test Vectors
Functional Description
This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols.
Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface.
Please consult the appropriate standards document for all external signaling.
TOP_SLAVE
This is the top level of the core. Its only purpose is to serve as a container to instantiate the transmit & receive modules. TOP_SLAVE is also where the generics are
located that configure the core. These parameters are then passed down to the TX & RX modules.
TOP_EGR_SLAVE & TOP_ING_SLAVE
These modules comprise the transmit and receive portions of the interface. They were developed so that they may be instantiated either separately in different
FPGAs or together in one FPGA. They use the common sub-modules FIFO_16 & FIFO_8, for simplicity and reliability.
EGR_UTOPIA3_SLAVE
The Egress Slave is responsible for replying to polls from the master in order to receive cells from the master device.
ING_UTOPIA3_SLAVE
The Ingress Slave is responsible for responding to the master in order to send cells to the master device.
FIFO_16 / FIFO_8
The FIFO module contains one FIFO per PHY polled (i.e. this module is instantiated N = number of PHY ports times in each direction. The FIFOs are created by
utilizing the available RAM resources in the FPGA. Additionally, two FIFO_16 modules (and hence 2x the RAMs) are instantiated to create a 32-bit wide FIFO for the
32-bit mode, however 2x the cells can be buffered. The FIFO may be operated in synchronous (same clock for read & write) and asynchronous (different clocks for
read & write) systems.
fifo_16/fifo_8
top_egr_slave
rd_data
rd_enb
rd_clk
rd_flag
TxClk
TxData
TxEnb_n
TxClav
TxSoc
TxPrty
TxAddr
reset_n
RxClk
RxData
RxEnb_n
RxClav
RxPrty
RxSoc
RxAddr
MDS8075
tx_utopia_slave
top_egr_slave
wr_data
wr_flag
wr_enb
wr_clk
fifo_16/fifo_8
top_ing_slave
rx_utopia_slave
top_ing_slave
Figure 1: Logic Symbol
Device Requirements
Family
Axcelerator
ProASIC3
ProASIC
PLUS
Device
COMB
AX250
A3PE600
APA150
38%
n/a
n/a
Utilization
SEQ
73%
n/a
n/a
Tiles
n/a
20%
52%
131 MHz
81 MHz
80 MHz
Performance
Table 1: Device Utilization and Performance
Verification and Compliance
The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error
signals. The test checks for errors at two stages in the testbench: when the cells are looped back through the Slave device (SIG_LOOP_ERROR_OUT) and upon
reading out of the Master device (SIG_ERROR_OUT).
Signal Descriptions
Signal
RD_DATA
RD_ENB
RD_CLK
RD_FLAG
RESET_N
WR_DATA
WR_FLAG
WR_ENB
WR_CLK
TXCLK
TXDATA
TXENB_N
TXCLAV
TXSOC
TXPRTY
TXADDR
RXCLK
RXDATA
RXENB_N
RXCLAV
RXPRTY
RXSOC
RXADDR
The following signal descriptions define the IO signals.
Width
8/16
1
1
1
1
8/16
1
1
1
1
8/16/32
1
1<N<4
1
1
8
1
8/16/32
1
1<N<4
1
1
8
Direction
Output
Input
Input
Output
Input
Input
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Input
Output
Output
Output
Input
Read data bus for the FIFO
Read enable signal for the FIFO
Read clock for the FIFO
FIFO packet available signal
Reset signal from user logic
Write data bus for FIFO
Write flag indicating if FIFO can accept another cell
Write enable signal for FIFO
System clock for all registers in this block
100 MHz utopia clock
Utopia data bus, 8, 16 or 32-bit selectable
Utopia enable signal used for throttle control
Utopia cell buffer available signal(s) used to indicate that the slave has room for a cell
Utopia start of cell signal used to flag the first byte/word in the cell
Utopia parity signal used for odd parity on TXDATA
Utopia address bus used for polling
100 MHz utopia clock
Utopia data bus, 8, 16 or 32-bit selectable
Utopia enable signal used for throttle control
Utopia cell buffer available signal(s) used to indicate that the slave has room for a cell
Utopia parity signal used for odd parity on TXDATA
Utopia start of cell signal used to flag the first byte/word in the cell
Utopia address bus used for polling
Table 2: Core I/O Signals
Description
Timing
Since the ATM Forum specification fully defines the line side of the UTOPIA Level 3 interface, timing for that is not replicated here. Instead, only user (FIFO) interface
timing information is presented here. The figure below shows the functional timing for FIFO reads and writes.
RD_CLK
RD_ADDR
A0
A1
A2
RD_ENB
D0
D1
D2
RD_DATA
WR_CLK
WR_ADDR
A0
A1
...
A52
A53
WR_ENB
WR_DATA
D0
D1
...
D52
D53
Figure 2: FIFO Timing
The top example shows where the last valid data word (LD) is clocked out relative to the deassertion of read enable. The bottom example shows read enable
responding to the assertion of read empty.
Recommended Design Experience
For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero Integrated Design Environment
(IDE) and preferably with Synplify and ModelSim.
Ordering Information
The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information.
Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at
any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not
make any commitment to update this information.
Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the
Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness
of any support or assistance provided to a user.
Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by
implication or otherwise under any patent or patent rights of Avnet Memec.
AvnetCore products are not intended for use in life support appliances, devices, or systems. Use of a AvnetCore product in such application without the written
consent of the appropriate Avnet Design officer is prohibited.
All trademarks, registered trademarks, or service marks are property of their respective owners.
Today is December 31, 2021, the last day of 2021. I should summarize what I have gained at EEworld on this day.Summarizing 2021, I feel that time has passed too quickly. In a blink of an eye, another ...
The influence of antenna structural parameters on antenna performanceThe parameter scanning analysis function of HFSS is used below to analyze the actual effects of the resonant length L of the invert...
Keil's code optimization is really annoying. Last night, the program failed when I selected -O0 optimization. Today, the program failed when I didn't select -O0 optimization. I don't know what to do....
1. Tools and materialsComputer, Windows systemESP8266 development boardmicro-USB cable1 LED light 1220Ω resistor 1breadboard + some jumpers
2. Hardware Connection3. Method steps1. Open the Zero Knowle...
The rk3568 chip is very powerful and can support many screen interfaces. The display interface support is very rich.The sunychip-rk3568 development board supports the screen with MIPI interface. The i...
The pipeline electromagnetic flowmeter is a commonly used flow measurement instrument that can be used to measure the volume flow of liquids such as salts, strong alkalis, and strong acids. It is wid...[Details]
The transformer characteristic comprehensive tester is also called transformer tester, volt-ampere characteristic comprehensive tester, transformer characteristic tester, current and voltage transfo...[Details]
Huatian Technology's 8 billion yuan packaging and testing project in Nanjing may have been put into production. Nanjing Daily previously reported that as of May 14, the under-construction portion of ...[Details]
The switching power supply has the advantages of small size, high efficiency, light weight, and low noise, and its application is becoming more and more extensive. When we design the battery charg...[Details]
Preface
In recent years, flash memory has been used in thousands of products, especially in industrial products such as mobile communications, MP3 music players, handheld PC managers, digital camer...[Details]
Recently, the temperature has been rising all over the country. With the March 8 Women's Day, it is obviously the best time to take your girlfriend on a spring outing. Giving your goddess a ro...[Details]
On October 22, the 2021 Beijing International Microelectronics Symposium and IC WORLD Conference was officially held. The conference will last for three days from the 22nd to the 24th. The conference...[Details]
As we cross 2020 and usher in 2021, at the end of the year and the beginning of the next year, IPO progress this week has also reached a small peak, with as many as 11 companies accepted and passed, ...[Details]
As the impact of future mobile travel changes, new energy technology development, consumer market recovery, and the accelerated implementation of relevant policies, regulations, and industry standard...[Details]
In industrial control, it is often necessary to transmit the data collected by the microcontroller to the PC for processing and display, and send control commands to the microcontroller based on the ...[Details]
The automotive industry is developing rapidly, the process of intelligence is accelerating, and advanced driver assistance and other functions are gradually being installed on mid- and low-end mode...[Details]
A new realme phone was recently registered with the Ministry of Industry and Information Technology. Its model number is RMX3310 and it is equipped with a Snapdragon 888 processor. The rear...[Details]
In December 2020, QuantumScape announced a breakthrough in the battery field. Its solid-state lithium metal battery can be charged to 80% in 15 minutes, and can extend the range of electric vehicles ...[Details]
1. Introduction
The interaction effectiveness between the modules of electric vehicles directly affects the driving efficiency and driving experience of the vehicle. Plug-in hybrid vehicles ca...[Details]
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
