V54C3256804VDUC7PC datasheet, PDF

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V54C3256804VDUC7PC: DescriptionSynchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA54, MO-210, FBGA-54; Categorystorage storage; File Size719KB，56 Pages; ManufacturerProMOS Technologies Inc

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V54C3256804VDUC7PC Overview

Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA54, MO-210, FBGA-54

V54C3256804VDUC7PC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	TFBGA, BGA54,9X9,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PBGA-B54
length	13 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	54
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA54,9X9,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.2 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm
Base Number Matches	1

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V54C3256(16/80/40)4VD

256Mbit SDRAM

(3.0~3.3) VOLT, TSOP II / FBGA PACKAGE

16M X 16, 32M X 8, 64M X 4

System Frequency (f

)

Clock Cycle Time (t

CK3

)

Clock Access Time (t

AC3

) CAS Latency = 3

Clock Access Time (t

AC2

) CAS Latency = 2

166 MHz

6 ns

5.4 ns

7PC

143 MHz

7 ns

5.4 ns

143 MHz

7 ns

5.4 ns

6 ns

Features

■

4 banks x 4Mbit x 16 organization

4 banks x 8Mbit x 8 organization

4 banks x16Mbit x 4 organization

High speed data transfer rates up to 166 MHz

Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

Single Pulsed RAS Interface

Data Mask for Read/Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 3

Programmable Wrap Sequence: Sequential or

Interleave

Programmable Burst Length:

1, 2, 4, 8, and full page for Sequential Type

1, 2, 4, 8 for Interleave Type

Multiple Burst Read with Single Write Operation

Automatic and Controlled Precharge Command

Random Column Address every CLK (1-N Rule)

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 54 Pin TSOP II, 60 Ball FBGA, 54

Ball FBGA

LVTTL Interface

Single (+3.0V~3.3 V)

±0.3

V Power Supply

Description

The V54C3256(16/80/40)4VD is a four bank Syn-

chronous DRAM organized as 4 banks x 4Mbit x 16,

4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The

V54C3256(16/80/40)4VD achieves high speed data

transfer rates up to 166 MHz by employing a chip

architecture that prefetches multiple bits and then

synchronizes the output data to a system clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

166 MHz is possible depending on burst length,

CAS latency and speed grade of the device.

■

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

T/S

•

Access Time (ns)

•

Power

•

7PC

•

Std.

•

Temperature

Mark

Blank

V54C3256(16/80/40)4VD Rev. 1.9 August 2008

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