GS8672D37AGE-375I datasheet, PDF

Datasheet> All Categories > storage> storage> GS8672D37AGE-375I

GS8672D37AGE-375I: DescriptionStandard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size839KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS8672D37AGE-375I Overview

Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8672D37AGE-375I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Preliminary

GS8672D19/37AE-400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II+

Burst of 4 ECCRAM

Clocking and Addressing Schemes

400 MHz–300 MHz

1.8 V V

1.5 V I/O

The GS8672D19/37AE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 4M x 18 has a 1M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable ECCRAMs with no On-Chip

ECC, which typically have an SER of 200 FITs/Mb or more.

SER quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the

Byte

Write Contol

section for further information.

SigmaQuad™ ECCRAM Overview

The GS8672D19/37AE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672D19/37AE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

Parameter Synopsis

-400

tKHKH

tKHQV

2.5 ns

0.45 ns

-375

2.66 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.00 5/2010

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8672D19/37AE-400/375/333/300

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate

I/O ECCRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write

transfers from Separate I/O ECCRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II+ ECCRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the

Truth Table

for

details.

SigmaQuad-II+ B4 ECCRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command.

Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 ECCRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.

Rev: 1.00 5/2010

5/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

DC relay delayed release circuit 4

Voice controlled power socket circuit

Constant voltage source thyristor control circuit

Power supply circuit diagram of PMV-P-14VC color display

Four-stage telecom filter circuit

Regarding "Circuit Design Based on Operational Amplifiers and Analog Integrated Circuits", there is a concept of "Pole" that is not clear: [i=s]This post was last edited by sunboy25 on 2020-10-8 23:15[/i]I would like to ask, is the place where I drew the red circle in the picture above correct as described in the book? Why do I feel that...; sunboy25 Analog electronics

RISC-V IDE MRS usage notes (Part 3): Improving floating-point calculation efficiency: MRS has built-in CH32V30X series chips. This series of chips supports FPU (floating point unit). If you want to turn it on, you need to enable the corresponding extension, as shown in the figure below...; Moiiiiilter MCU

Pan it STM32H750 3 (lan8720 Ethernet test --iperf): [font=宋体][size=4] When debugging lan8720 hardware, you need to check whether the ground pad is cold soldered, whether the internal voltage regulator 1.2V has output, and whether it has output 50M freq...; RCSN stm32/stm8

Another question about the matrix keyboard: I used STM32 to write a matrix keyboard program. It was originally a query method, but now it has been changed to a timer method.Schematic diagram:void KEY_Init(void){GPIO_InitTypeDef GPIO_InitStructu...; chenbingjy stm32/stm8

Transmit power measurement method: Transmit power is the main technical indicator of radio transmission equipment and one of the technical indicators that radio management departments need to test. This article mainly introduces severa...; Aguilera RF/Wirelessly

My Journey of MCU Development (VI): While I was working hard on ucLinux, I also became interested in embedded real-time operating systems. The first real-time operating system I came into contact with was uC/OSⅡ. At that time, I started...; bigbat Talking about work

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components