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GS864418E-166IVT

Description
Cache SRAM, 4MX18, 7ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
Categorystorage    storage   
File Size529KB,33 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS864418E-166IVT Overview

Cache SRAM, 4MX18, 7ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS864418E-166IVT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeBGA
package instructionLBGA,
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time7 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 codeR-PBGA-B165
length17 mm
memory density75497472 bit
Memory IC TypeCACHE SRAM
memory width18
Number of functions1
Number of terminals165
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4MX18
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum supply voltage (Vsup)2 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width15 mm
Base Number Matches1
GS864418/36E-xxxV
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V or 2.5 V core power supply and I/O
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 165-bump BGA package available
4M x 18, 2M x 36
72Mb S/DCD Sync Burst SRAMs
250 MHz–133MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
Functional Description
Applications
The GS864418/36E-xxxV is a
75,497,472
-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
SCD and DCD Pipelined Reads
The GS864418/36E-xxxV is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS864418/36E-xxxV operates on a 1.8 V or 2.5 V power
supply. All inputs are 1.8 V and 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 1.8 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
3.0
4.0
385
450
6.5
6.5
265
290
3.0
4.4
360
415
6.5
6.5
265
290
3.0
5.0
335
385
6.5
6.5
265
290
3.0
6.0
305
345
8.0
8.0
255
280
3.3
6.7
295
325
8.5
8.5
240
265
3.5
7.5
265
295
8.5
8.5
225
245
ns
ns
mA
mA
ns
ns
mA
mA
Flow
Through
2-1-1-1
Rev: 1.07a 10/2009
1/33
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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