PI74FCT374/2374T and PI74FCT574/2574T Logic Block Diagram
D
0
CP
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
D
1
D
2
D
3
D
4
D
5
D
6
D
7
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1
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Ω
(25Ω
PI74FCT374T/534T/574T
PI74FCT374T/534T/574T
(25Ω Series) P174FCT2374T/2574T
Ω
Octal D Registers (3-State)
Series) PI74FCT2374T/2574T
Product Features:
Fast CMOS Octal D
Registers (3-State)
PI74FCT374/534/574/2374/2574T is pin compatible with bipolar
FAST Series at a higher speed and lower power
consumption
25Ω series resistor on all outputs (FCT2XXX only)
TTL input and output levels
Low ground bounce outputs
Extremely low static power
Hysteresis on all inputs
Industrial operating temperature range: 40°C to +85°C
Packages available:
20-pin 173 mil wide plastic TSSOP (L)
20-pin 300 mil wide plastic DIP (P)
20-pin 150 mil wide plastic QSOP (Q)
20-pin 150 mil wide plastic TQSOP (R)
20-pin 300 mil wide plastic SOIC (S)
Product Description:
Pericom Semiconductors PI74FCT series of logic circuits are pro-
duced in the Companys advanced 0.6/0.8 micron CMOS technology,
achieving industry leading speed grades. All PI74FCT2XXX devices
have a built-in 25 ohm series resistor on all outputs to reduce noise
resulting from reflections, thus eliminating the need for an external
terminating resistor.
The PI74FCT374T/534T/574T and P174FCT2374T/2574T are
8-bit wide octal registers designed with eight D-type flip-flops with
a buffered common clock and buffered 3-state outputs. When
output enable (OE) is LOW, the outputs are enabled. When OE is
HIGH, the outputs are in the high impedance state. Input data
meeting the setup and hold time requirements of the D inputs is
transferred to the O outputs on the LOW-to-HIGH transition of the
clock input.
Device models available upon request.
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
PI74FCT534T Logic Block Diagram
D
0
CP
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
1
PS2016B
02/22/00
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT374T/534T/574T
(25Ω Series) P174FCT2374T/2574T
Ω
Octal D Registers (3-State)
PI74FCT374/2374T Product Pin Configuration
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
20
2
19
3
20-PIN
18
4
L20
17
5
P20
16
Q20
15
6
R20
14
7
S20
13
8
9
12
10
11
Product Pin Description
Pin Name
OE
CP
D
0
-D
7
O
0
-O
7
O
0
-O
7
GND
V
CC
Description
Output Enable Input (Active LOW)
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition
Data Inputs
3-State Outputs (true)
3-State Outputs (inverted)
Ground
Power
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
PI74FCT534T Product Pin Configuration
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
20
2
19
20-PIN
18
3
L20
17
4
P20
16
5
Q20
15
6
R20
14
7
S20
13
8
9
12
10
11
PI74FCT534T Truth Table
(1)
Function
OE
H
H
L
L
H
H
Inputs
CP
L
H
↑
↑
↑
↑
D
N
X
X
L
H
L
H
Outputs
O
N
Z
Z
H
L
Z
Z
Internal
Q
N
NC
NC
L
H
L
H
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
High-Z
Load Register
PI74FCT374/574/2374/2574T Truth Table
(1)
Function
High-Z
Load Register
OE
H
H
L
L
H
H
Inputs
CP
L
H
↑
↑
↑
↑
D
N
X
X
L
H
L
H
Outputs
O
N
Z
Z
L
H
Z
Z
Internal
Q
N
NC
NC
H
L
H
L
PI74FCT574/2574T Product Pin Configuration
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
20
2
19
20-PIN
18
3
L20
17
4
P20
16
5
Q20
15
6
R20
7
14
S20
8
13
9
12
10
11
Vcc
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CP
1.
H = High Voltage Level
L = Low Voltage Level
X = Dont Care
Z = High Impedance
NC = No Change
↑=
LOW-to-HIGH transition
2
PS2016B
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Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT374T/534T/574T
(25Ω Series) P174FCT2374T/2574T
Ω
Octal D Registers (3-State)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................................. 65°C to +150°C
Ambient Temperature with Power Applied ................................. -40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V
DC Input Voltage ......................................................................... 0.5V to +7.0V
DC Output Current ................................................................................... 120 mA
Power Dissipation ......................................................................................... 0.5W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 5.0V ± 5%)
Parameters Description
V
OH
V
OL
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OFF
I
OS
V
H
Output HIGH Voltage
Output LOW Current
Output LOW Current
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Clamp Diode Voltage
Power Down Disable
Short Circuit Current
Input Hysteresis
V
CC
= Min., I
IN
= 18 mA
V
CC
= GND, V
OUT
= 4.5V
V
CC
= Max.
(3)
, V
OUT
= GND
60
Test Conditions
(1)
V
CC
= Min., V
IN
= V
IH
or V
IL
V
CC
= Min., V
IN
= V
IH
or V
IL
V
CC
= Min., V
IN
= V
IH
or V
IL
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= M
AX
.
V
IN
= V
CC
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
0.7
120
200
I
OH
= 15.0 mA
I
OL
= 64 mA
I
OL
= 12 mA (25Ω Series)
2.0
0.8
1
1
1
1
1.2
100
Min. Typ
(2)
Max. Units
2.4
3.0
0.3
0.3
0.55
0.50
V
V
V
V
V
µA
µA
µA
µA
V
µA
mA
mV
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(4)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
6
8
Max.
10
12
Units
pF
pF
3
PS2016B
02/22/00
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT374T/534T/574T
(25Ω Series) P174FCT2374T/2574T
Ω
Octal D Registers (3-State)
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power
Supply Current
Supply Current per
Input @ TTL HIGH
Supply Current per
Input per MHz
(4)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
CP
= 10 MH
Z
50% Duty Cycle
OE = GND
f
I
= 5 MH
Z
One Bit Toggling
V
CC
= Max.,
Outputs Open
f
CP
= 10 MH
Z
50% Duty Cycle
OE = GND
Eight Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
Test Conditions
(1)
V
IN
= GND or V
CC
V
IN
= 3.4V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
0.5
0.15
Max.
500
2.0
0.25
Units
µA
mA
mA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
1.5
2.0
3.5
(5)
5.5
(5)
mA
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
3.8
6.0
7.3
(5)
16.3
(5)
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4 V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
4
PS2016B
02/22/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT374T/534T/574T
(25Ω Series) P174FCT2374T/2574T
Ω
Octal D Registers (3-State)
PI74FCT374/2374T Switching Characteristics over Operating Range
374T/2374T
Com.
374AT/2374AT
Com.
Max
Min
Max
Min
374CT/2374CT
Com.
Max
Min
374DT/2374DT
Com.
Max
Units
Parameters
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Description
Propagation Delay
CP to O
N
Output Enable Time
OE to O
N
Output Disable Time
(3)
OE to O
N
Setup Time HIGH or
LOW, D
N
to CP
Hold Time HIGH or
LOW, D
N
to CP
CP Pulse Width
(3)
HIGH orLOW
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
Min
2.0
1.5
1.5
2.0
1.5
7.0
10.0
12.5
8.0
2.0
1.5
1.5
2.0
1.5
5.0
6.5
6.5
5.5
2.0
1.5
1.5
2.0
1.5
5.0
5.2
5.5
5.0
2.0
1.5
1.5
2.0
1.0
3.0
4.5
5.5
5.0
ns
ns
ns
ns
ns
ns
PI74FCT534T Switching Characteristics over Operating Range
534T
Com.
534AT
Com.
Max
Min
Max
Min
534CT
Com.
Max
Min
534DT
Com.
Max
Units
Parameters
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Description
Propagation Delay
CP to O
N
Output Enable Time
OE to O
N
Output Disable Time
(3)
OE to O
N
Setup Time HIGH or
LOW, D
N
to CP
Hold Time HIGH or
LOW, D
N
to CP
CP Pulse Width
(3)
HIGH orLOW
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
Min
2.0
1.5
1.5
2.0
1.5
7.0
10.0
12.5
8.0
2.0
1.5
1.5
2.0
1.5
5.0
6.5
6.5
5.5
2.0
1.5
1.5
2.0
1.5
5.0
5.2
5.5
5.0
2.0
1.5
1.5
2.0
1.0
3.0
4.5
5.5
5.0
ns
ns
ns
ns
ns
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
5
PS2016B
02/22/00