CY7C1462AV33-250AXCT datasheet, PDF

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CY7C1462AV33-250AXCT: DescriptionZBT SRAM, 2MX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100; Categorystorage storage; File Size506KB，27 Pages; ManufacturerCypress Semiconductor

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CY7C1462AV33-250AXCT Overview

ZBT SRAM, 2MX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

CY7C1462AV33-250AXCT Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e3/e4
length	20 mm
memory density	37748736 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
Base Number Matches	1

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined SRAM with NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• 3.3V power supply

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• CY7C1460AV33, CY7C1462AV33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1464AV33

available in lead-free and non-lead-free 209-ball FBGA

package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are

3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back

Read/Write operations with no wait states. The

CY7C1460AV33/CY7C1462AV33/CY7C1464AV33

are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read

transitions.

The

CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin

compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

for

CY7C1464AV33,

–BW

for

(BW

–BW

CY7C1460AV33 and BW

–BW

for CY7C1462AV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram-CY7C1460AV33 (1M x 36)

A0, A1, A

MODE

CLK

CEN

ADDRESS

A1'

A0'

BURST

LOGIC

ADV/LD

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

MEMORY

ARRAY

DQs

DQP

INPUT

CE1

CE2

CE3

READ LOGIC

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05353 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 22, 2006

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CY7C1462AV33-250AXCT Related Products

	CY7C1462AV33-250AXCT	CY7C1462AV33-200AXCT	CY7C1460AV33-200BZXI
Description	ZBT SRAM, 2MX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100	ZBT SRAM, 2MX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100	ZBT SRAM, 1MX36, 3.2ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
Parts packaging code	QFP	QFP	BGA
package instruction	LQFP,	LQFP,	LBGA, BGA165,11X15,40
Contacts	100	100	165
Reach Compliance Code	unknown	unknown	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	2.6 ns	3.2 ns	3.2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PBGA-B165
JESD-609 code	e3/e4	e3/e4	e1
length	20 mm	20 mm	17 mm
memory density	37748736 bit	37748736 bit	37748736 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	18	18	36
Number of functions	1	1	1
Number of terminals	100	100	165
word count	2097152 words	2097152 words	1048576 words
character code	2000000	2000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C
organize	2MX18	2MX18	1MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.4 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V	3.63 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN/NICKEL PALLADIUM GOLD	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	GULL WING	GULL WING	BALL
Terminal pitch	0.65 mm	0.65 mm	1 mm
Terminal location	QUAD	QUAD	BOTTOM
width	14 mm	14 mm	15 mm
Base Number Matches	1	1	-
Maker	-	Cypress Semiconductor	Cypress Semiconductor

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