Intel
®
LXT3108
Octal T1/E1/J1 Long/Short Haul Line Interface Unit
Preliminary Datasheet
The Intel
®
LXT3108 is an octal 3.3 V Long/Short Haul (LH/SH) T1/E1/J1 Line Interface Unit
(LIU). This flexible LIU allows for the design of T1/E1/J1 LH/SH multi-service cards with a
single design and requires no external component changes and can be configured on a
per-port basis through internal registers. Intel’s proven design makes the LXT3108 the perfect
device for high-density T1/E1/J1 applications. To increase network reliability, the LXT3108
incorporates a DSP-based architecture with features, such as Intel
®
Hitless Protection Switching
(Intel
®
HPS) and Intel
®
Pulse Template Matching (Intel
®
PTM). The DSP-based architecture is
less sensitive to power supply and temperature variations and allows the LIU to adapt to varying
line conditions. Intel
®
HPS allows for the design of 1+1 redundant cards without the use of
relays, and has the ability to switch from one card to another, without loss of frame
synchronization. Intel
®
PTM software allows the transmitter to shape the output pulse to meet
various board conditions, without the need to change any external components.
Applications
■
■
■
■
Voice-over-packet gateways
Integrated Multi-service Access Platforms
(IMAPs)
Integrated Access Devices (IADs)
Inverse multiplexing for ATM (IMA)
■
■
■
■
Wireless base stations
Routers
Frame relay access devices
CSU/DSU equipment
Product Features
■
■
■
■
■
■
Intel
®
HPS for 1+1 protection without
relays
Intel
®
PTM software for pulse output
adjustment through software without
component or board change
Interfaces with the Intel
®
IXF3208, Octal
T1/E1/J1 Framer with Intel
®
On-chip
Performance Report Messaging
(Intel
®
On-Chip PRM)
T1 (100 Ohm), E1 (75 and 120 Ohm), J1
(110 Ohm) termination and LH/SH
selectable per port through software
without component change
Receiver sensitivity exceeds 36 dB @ 772
KHz and 38 dB @ 1024 KHz of cable
attenuation providing margin for board and
cable variations
3.3 V power supply with 5 V tolerant
inputs
■
■
■
■
■
■
On-chip Clock Adaptor (CLAD) that
allows one master clock for T1/E1/J1
applications (1X, 2X, 4X, or 8X T1 or E1
clock)
16-bit BPV/Excess Zero counters per port
B8ZS/HDB3 encoders and decoders, and
unipolar/bipolar I/O modes selectable per
port
Digital Jitter Attenuator (DJA) in either
receive or transmit path
Will substantially conform to publicly
available specifications in ANSI T1.102,
T1.403, and T1.408; ITU I.431, CTR12/13,
G.703, G.736, G.775, and G.823;
ETSI 300-166 and 300-233; and AT&T
Pub 62411
Available in a 17 x 17 mm 256 PBGA
(LXT3108 BE), or 28 x 28 mm 208 QFP
(LXT3108 HE) package
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
LXT3108 Octal T1/E1/J1 Long/Short Haul Line Interface Unit may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-
4725, or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2003
2
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
Contents
Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Pin Assignments
......................................................................................................................... 13
Signal Descriptions
..................................................................................................................... 15
Intel
®
LXT3108 LIU Nomenclature
.............................................................................................. 28
Functional Description................................................................................................................
29
Port Descriptions.........................................................................................................................
31
Software Support.........................................................................................................................
34
Initialization
..................................................................................................................................35
7.1
7.2
8.0
CLAD Initialization .............................................................................................................. 35
Reset Operation.................................................................................................................. 35
Power Supply Requirements
...................................................................................................... 36
8.1
8.2
5 V Tolerant I/O Pins .......................................................................................................... 36
Layout Considerations ........................................................................................................36
8.2.1 Ground Plane......................................................................................................... 36
8.2.2 Analog Power Supply ............................................................................................37
8.2.3 Digital Power Supply.............................................................................................. 37
9.0
Transmitter...................................................................................................................................
38
9.1
Transmit Line Interface ....................................................................................................... 39
9.1.1 Transmit Impedance Termination .......................................................................... 40
9.1.2 Transmit Return Loss Performance .......................................................................40
9.1.2.1 Intel
®
Pulse Template Matching (Intel
®
PTM) ........................................41
Transmit Digital Interface .................................................................................................... 42
9.2.1 Transmit Idle Operation and Three-stating Drivers................................................ 42
9.2
10.0 Receiver........................................................................................................................................
44
10.1
10.2
10.3
Master Reference Clock ..................................................................................................... 44
Receiver Digital Interface.................................................................................................... 44
10.2.1 Receiver Idle Conditions ........................................................................................ 44
Receiver Line Interface ....................................................................................................... 45
10.3.1 Receive Termination Impedance ........................................................................... 45
10.3.2 Programming the Intel
®
LXT3108 .......................................................................... 45
10.3.3 Guidelines for Programming the Intel
®
LXT3108 Receiver.................................... 46
10.3.4 Receiver Operation with Transients.......................................................................46
10.3.5 Receiver Sensitivity Programming .........................................................................46
10.3.5.1 Receiver Monitor Mode .......................................................................... 47
Receiver Status Information ............................................................................................... 48
10.4
11.0 Jitter Attenuation (JA)
................................................................................................................. 49
11.1
Digital Jitter Attenuator (DJA) Status .................................................................................. 49
12.0 Network Control and Maintenance Functions
.......................................................................... 50
12.1
Diagnostic Modes ...............................................................................................................50
3
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
Contents
12.2
12.3
12.1.1 In-Band Network Loop Up or Down Code Generator/Detector.............................. 50
12.1.2 Analog Loopback ................................................................................................... 50
12.1.3 Digital Loopback .................................................................................................... 51
12.1.4 Remote Loopback.................................................................................................. 51
12.1.5 Transmit All Ones (TAOS) ..................................................................................... 52
Line Coding......................................................................................................................... 53
12.2.1 Alternate Mark Inversion (AMI) .............................................................................. 54
12.2.1.1 Bipolar with Eight Zero Substitution (B8ZS)........................................... 54
12.2.1.2 High Density Bipolar Three (HDB3) ....................................................... 55
Network Maintenance Functions ........................................................................................ 55
12.3.1 Loss Of Signal (LOS)............................................................................................. 55
12.3.1.1 Operation of USER LOS with Amplitude Detection ............................... 57
12.3.1.2 Operation of USER LOS with Marks Density Detection......................... 58
12.3.2 Alarm Indication Signal (AIS)................................................................................. 58
12.3.3 NLOOP Status ....................................................................................................... 59
12.3.3.1 T1 AMI/B8ZS BPVs ............................................................................... 59
12.3.3.2 E1 AMI/HDB3 BPVs............................................................................... 59
12.3.3.3 Excess Zeros (EXZ)............................................................................... 60
12.3.4 Monitoring BPV and EXZ Line Coding Violations .................................................. 60
13.0 Host Interface...............................................................................................................................61
13.1
Supported Processors and Connections ............................................................................ 61
13.1.1 MPC860................................................................................................................. 61
13.1.2 M68302* ................................................................................................................ 62
13.1.3 Intel
®
i960
®
/i486
TM
................................................................................................ 62
Interrupts............................................................................................................................. 63
13.2.1 Interrupt Enabling .................................................................................................. 63
13.2.2 Interrupt Clearing ................................................................................................... 63
13.2
14.0 Register Definitions.....................................................................................................................
65
14.1
14.2
Global Registers ................................................................................................................. 65
Port Page Register Bank (PPRB) ....................................................................................... 67
15.0 JTAG Boundary Scan..................................................................................................................
81
15.1
15.2
15.3
Architecture......................................................................................................................... 81
TAP Controller .................................................................................................................... 81
JTAG Register Description ................................................................................................. 84
15.3.1 Boundary Scan Register (BSR) ............................................................................. 84
15.3.2 Device Identification Register (IDR)....................................................................... 84
15.3.3 Bypass Register (BYR).......................................................................................... 84
15.3.4 Instruction Register (IR)......................................................................................... 84
16.0 Test Specifications......................................................................................................................
86
16.1
16.2
Microprocessor Interface Timing Diagrams ........................................................................ 97
Referenced Standards...................................................................................................... 104
17.0 Mechanical Specification..........................................................................................................
105
18.0 Glossary
..................................................................................................................................... 107
4
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
Contents
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Intel
®
LXT3108 LIU Block Diagram............................................................................................. 11
Intel
®
LXT3108 HE 208 Pin Assignment .................................................................................... 13
Intel
®
LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments ........................................14
T1/E1/J1 LIU Block Diagram ...................................................................................................... 29
Intel
®
LXT3108 LIU Port Block Diagram .....................................................................................31
Intel
®
LXT3108 LIU Port Circuit .................................................................................................. 32
Transmitter Circuit for Twisted Pair and Coaxial Cable .............................................................. 33
Diode Protection Network When Inputs Power Up Before Supplies........................................... 36
50% AMI Encoding ..................................................................................................................... 38
Typical Transmitter Interface Connections ................................................................................. 39
T1, T1.102 Mask Templates ....................................................................................................... 41
Transmit Interface Timing ........................................................................................................... 42
TCLK Power Down Timing ......................................................................................................... 43
Typical Receiver Interface .......................................................................................................... 45
Jitter Attenuation Loop ...............................................................................................................49
Analog Loopback ........................................................................................................................ 51
Digital Loopback ......................................................................................................................... 51
Remote Loopback....................................................................................................................... 52
TAOS Data Path ......................................................................................................................... 52
TAOS with Digital Loopback ....................................................................................................... 52
TAOS with Analog Loopback...................................................................................................... 53
Interrupt Processing FlowChart .................................................................................................. 64
Intel
®
LXT3108 LIU JTAG Architecture....................................................................................... 81
JTAG State Diagram................................................................................................................... 83
Transmit Clock Timing Diagram .................................................................................................90
Receive Clock Timing Diagram .................................................................................................. 92
Intel
®
LXT3108 LIU Output Jitter for CTR12/13 Applications ..................................................... 93
JTAG Timing............................................................................................................................... 93
E1, G.703 Mask Templates ........................................................................................................94
Intel
®
LXT3108 LIU Jitter Tolerance Performance...................................................................... 95
Intel
®
LXT3108 LIU Jitter Transfer Performance ........................................................................ 96
MPC860 Write Timing................................................................................................................. 97
MPC860 Read Timing ................................................................................................................ 98
M68302 Write Timing.................................................................................................................. 99
M68302 Read Timing ............................................................................................................... 100
Intel
®
i486
TM
/i960
®
Non-muxed Mode Write Timing................................................................. 101
Intel
®
i960
®
Muxed Mode Write Timing .................................................................................... 101
Intel
®
i486
TM
/i960
®
Non-muxed Mode Read Timing................................................................. 102
Intel
®
i960
®
Muxed Mode Read Timing .................................................................................... 103
Intel
®
LXT3108 LIU 256 PBGA Mechanical Specification ........................................................ 105
Intel
®
LXT3108 LIU 208 Pin QFP Mechanical Specifications ..................................................106
Preliminary Datasheet
Document Number: 249543
Revision #: 008
Rev. Date: January 08, 2003
5
DSP and ARM Processors
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