WE32K32-XXX
HI-RELIABILITY PRODUCT
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
s
Access Times of 80*, 90, 120, 150ns
s
MIL-STD-883 Compliant Devices Available
s
Packaging:
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square,
3.56mm (0.140") height (Package 510). Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)
• 66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400)
s
Data Retention at 25°C, 10 Years
s
Write Endurance, 10,000 Cycles
s
Organized as 32Kx32; User Configurable 64Kx16 or 128Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
Automatic Page Write Operation
s
Page Write Cycle Time: 10ms Max
s
Data Polling for End of Write Detection
s
Hardware and Software Data Protection
s
TTL Compatible Inputs and Outputs
s
5 Volt Power Supply
s
Low Power CMOS, 10mA Standby Typical
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
* 80ns speed is not fully characterized and is subject to change or
cancellation without notice.
FIG. 1
PIN CONFIGURATION FOR WE32K32N-XH1X
TOP VIEW
PIN DESCRIPTION
34
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
56
1
I/O
8
I/O
9
I/O
10
A
13
A
14
NC
NC
NC
I/O
0
I/O
1
I/O
2
11
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
23
I/O
0-31
Data Inputs/Outputs
A
0-14
WE
1-4
CS
1-4
OE
V
CC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
66
8
8
8
GND
NC
BLOCK DIAGRAM
W E
1
CS
1
OE
A
0-14
32K x 8
32K x 8
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
32K x 8
32K x 8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
June 1999 Rev. 2
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE32K32-XXX
FIG. 2
PIN CONFIGURATION FOR WE32K32-XG2UX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-14
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
WE
1-4
CS
1-4
OE
V
CC
GND
NC
WE
2
WE
3
WE
4
CS
1
OE
CS
2
V
CC
A
11
A
12
A
13
A
14
BLOCK DIAGRAM
W E
1
CS
1
OE
A
0-14
32K x 8
32K x 8
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
NC
NC
NC
NC
NC
NC
0.940"
32K x 8
32K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
WE32K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE and A9
Symbol
T
A
T
STG
V
G
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to +13.5
Unit
°C
°C
V
V
CS
H
L
L
X
X
X
OE
X
L
H
H
X
L
TRUTH TABLE
WE
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
Min
4.5
2.0
-0.5
-55
-40
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
Parameter
CAPACITANCE
(T
A
= 25° C)
Symbol
C
AD
C
OE
C
CS
C
WE
C
I/O
Condition
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
Max
50
20
20
20
Unit
pF
pF
pF
pF
Address Input Capacitance
OE Capacitance
CS
1-4
Capacitance
WE
1-4
Capacitance
Data I/O Capacitance
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current x 32 Mode
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO x 32
I
CC x 32
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz
CS = V
IH
, OE = V
IH
, f = 5MHz
I
OL
= 2.1mA, V
CC
= 4.5V
I
OH
= -400µA, V
CC
= 4.5V
2.4
-80
Min Max
10
10
320
2.5
0.45
2.4
-90
Min Max
10
10
250
2.5
0.45
2.4
-120
Min Max
10
10
200
2.5
0.45
2.4
-150
Units
Min Max
10
µA
10
150
2.5
0.45
µA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
FIG. 3
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE32K32-XXX
WRITE
A write cycle is initiated when OE is high and a low pulse is on
WE or CS with CS or WE low. The address is latched on the
falling edge of CS or WE whichever occurs last. The data is
latched by the rising edge of CS or WE, whichever occurs first.
A byte write operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 150
µsec
delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150
µsec
time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
AC WRITE CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C to +125°C)
WRITE CYCLE
Write Cycle Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE or CS)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
Symbol
t
WC
t
AS
t
WP
t
CS
t
AH
t
DH
t
CSH
t
DS
t
WPH
t
OES
t
OEH
0
100
0
50
0
0
50
50
10
10
Min
-80
Max
10
0
100
0
50
0
0
50
50
10
10
Min
-90
Max
10
30
150
0
100
10
0
100
50
10
10
Min
-120
Max
10
30
150
0
100
10
0
100
50
10
10
Min
-150
Max
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
WE32K32-XXX
FIG. 4
WRITE WAVEFORMS
WE CONTROLLED
t
WC
OE
t
OES
ADDRESS
t
AS
CS
1-4
t
CS
WE
1-4
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
FIG. 5
WRITE WAVEFORMS
CS CONTROLLED
t
WC
OE
t
OES
ADDRESS
t
AS
WE
1 - 4
t
CS
CS
1 - 4
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
5
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
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