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Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• Single 2.5V
±0.2V
Power Supply
• 2.5V SSTL-2 compatible I/O
• Burst Length (B/L) of 2, 4, 8
• 2,2.5,3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• DLL aligns DQ & DQS transitions with CLK
transition
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
EM42AM1684RTA
256Mb (4M
×
4Bank
×
16)
Double DATA RATE SDRAM
Description
The EM42AM1684RTA is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 268,435,456 bits which
organized as 4Meg words x 4 banks by 16 bits.
The 256Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
Ordering Information
Part No
EM42AM1684RTA-75F
EM42AM1684RTA-6F
EM42AM1684RTA-5F
Organization
16M X 16
16M X 16
16M X 16
Max. Freq
133MHz @CL25
166MHz @CL25
200MHz @CL3
Package
66pin TSOP(ll)
66pin TSOP(ll)
66pin TSOP(ll)
Grade
Commercial
Commercial
Commercial
Pb
Free
Free
Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/19
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Pin Assignment
EM42AM1684RTA
66pin TSOP-II / (400mil
×
875mil) / (0.65mm Pin pitch)
Jul. 2006
2/19
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Pin Description (Simplified)
Pin
Name
45,46
CLK,/CLK
EM42AM1684RTA
Function
(System Clock)
Clock input active on the Positive rising edge except for DQ and
DM are active on both edge of the DQS.
CLK and /CLK are differential clock inputs.
(Chip Select)
/CS enables the command decoder when ”L” and disable the
command decoder when “H”.The new command are over-
Looked when the command decoder is disabled but previous
operation will still continue.
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
When deactivate the clock,CKE low signifies the power down or
self refresh mode.
(Address)
Row address (A0 to A12) and Calumn address (CA0 to CA8) are
multiplexed on the same pin.
CA10 defines auto precharge at Calumn address.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK with
/RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Data Input/Output)
Data Inputs and Outputs are synchronized with both edge of DQS.
(Data Input/Output Mask)
DM controls data inputs.LDM corresponds to the data on
DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15.
(Data Input/Output)
Data inputs and outputs are multiplexed on the same pin.
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
(No Connection/Reserved for Future Use)
This pin is recommended to be left No Connection on the device.
(Input)
SSTL-2 Reference voltage for input buffer.
24
/CS
44
CKE
28~32,35~42
A0~A12
26, 27
23
BA0, BA1
/RAS
22
/CAS
21
16/51
20/47
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
1,18,33/
34,48,66
3, 9, 15, 55.61/
6, 12, 52, 58,64
14,17,19,25,43,
50,53
49
/WE
LDQS/UDQS
LDM/UDM
DQ0~DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC/RFU
V
REF
Jul. 2006
3/19
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Absolute Maximum Rating
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
OP
T
STG
P
D
I
OS
Item
Input, Output Voltage
Power Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Short Circuit Current
EM42AM1684RTA
Rating
-0.3 ~ +3.6
-0.3 ~ +3.6
Commercial
0 ~ +70
Extended
N/A
-55 ~ +150
1
50
Units
V
V
°
C
°
C
W
mA
Note:
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (V
CC
=2.5V, f=1MHz, T
A
=25°
C)
Symbol
C
CLK
C
I
C
O
Parameter
Clock Capacitance(CLK,/CLK)
Input Capacitance for CKE, Address, /CS,
/RAS, /CAS, /WE
DM,Data&DQS Input/Output Capacitance
Min.
2
2
4
Typ.
Max.
3
3
5
Units
pF
pF
pF
Recommended DC Operating Conditions (T
A
=-0° ~+70°C)
C
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
Parameter
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
I/O Logic high Voltage
I/O Termination Voltage
Input Logic High Voltage
Input Logic Low Voltage
Min.
2.3
2.3
1.15
V
REF
-0.04
V
REF
+0.18
-0.3
Typ.
2.5
2.5
1.25
Max.
2.7
2.7
1.35
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.18
Units
V
V
V
V
V
V
Jul. 2006
4/19
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Recommended DC Operating Conditions
(V
DD
=2.5V±0.2V, T
A
=0°C ~ 70°
C)
Symbol
I
DD1
I
DD2P
Parameter
Operating Current
(Note 1)
EM42AM1684RTA
Test Conditions
Burst length=2,
t
RC
≥t
RC
(min.), I
OL
=0mA,
One bank active
CKE≤V
IL
(max.), t
CK
=min
CKE≥V
IL
(min.), t
CK
=min,
/CS≥V
IH
(min.)
Input signals are changed one time
during 2 clks
CKE≤V
IL
(max.), t
CK
=min
CKE≥V
IH
(min.), t
CK
=min,
/CS≥V
IH
(min.)
Input signals are changed one time
during 2 clks
READ
t
CK
≥
t
CK
(min.), I
OL
=0mA,
All banks active
WRITE
t
RC
≥
t
RFC
(min.), All banks active
CKE≤0.2V
Max.
-5
120
-6
120
20
-75
110
Units
mA
mA
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-power Down Mode
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
Operating Current (Burst
(Note 2)
Mode)
Refresh Current
(Note 3)
I
DD2N
45
mA
I
DD3P
21
mA
I
DD3N
75
200
200
225
3
mA
I
DD4
I
DD5
I
DD6
mA
mA
mA
Self Refresh Current
*All voltages referenced to V
SS
.
Note 1:
I
DD1
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 2:
I
DD4
depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during t
CK
(min.)
Note 3:
Min. of t
RFC
(Auto refresh Row Cycle Times) is shown at AC Characteristics.
Recommended DC Operating Conditions (Continued)
Symbol
I
IL
I
OL
V
OH
V
OL
I
OHW
I
OLw
Parameter
Input Leakage Current
Output Leakage Current
High Level Output Voltage
Low Level Output Voltage
Output current
half-strength Driver
Test Conditions
0≤V
I
≤V
DDQ
, V
DDQ
=V
DD
All other pins not under test=0V
0≤V
O
≤V
DDQ
, D
OUT
is disabled
I
O
=-16.8mA
I
O
=+16.8mA
V
OUT=
V
DDQ
-0.763V; min.V
REF
V
TT
V
OUT=
0.763V ; max. V
REF
V
TT
-9
9
Min.
-5
-5
V
DDQ
-0.373
0.373
Max.
+5
+5
Units
uA
uA
V
V
mA
mA
Jul. 2006
5/19
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