Blackfin
®
Embedded Processor
ADSP-BF538/ADSP-BF538F
FEATURES
Up to 533 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of program-
ming and compiler friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.25 V core V
DD
with on-chip voltage regulation
2.5 V to 3.3 V I/O V
DD
Up to 3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI
®
and external
memory
PERIPHERALS
Parallel peripheral interface (PPI) supporting ITU-R 656 video
data formats
Four dual-channel, full-duplex synchronous serial ports,
supporting 16 stereo I
2
S
®
channels
Two DMA controllers supporting 26 peripheral DMAs
Four memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three 32-bit timer/counters with PWM support
Three UARTs with support for IrDA
®
Two TWI controllers compatible with I
2
C
®
industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of 0.5 to 64 frequency multiplication
Debug/JTAG interface
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K 16-bit or 256K 16-bit of flash memory
(ADSP-BF538F only)
Memory management unit providing memory protection
V OLT A GE R E GU LA T OR
JTA G T ES T A N D E M U LA TIO N
PE R IP H E R A L A C C E S S B U S
TW I0-1
C A N 2.0B
GP IO
PO RT
C
B
DM A
C O N TR OL LE R1
DMA ACCESS BUS 1
IN TE R R U P T
C ON T R OLL ER
PERIPHERAL ACCESS BUS
W A T C HD OG
TIM E R
R TC
PP I
G PIO
S P I1-2
L1
IN ST R UC TION
M EM O R Y
L1
DATA
M EM O RY
DM A
C ON T R OL LER 0
DMA ACCESS BUS 0
GP IO
P OR T
D
TIM ER 0-2
SP I0
U A RT0
SP ORT 0-1
U A R T1-2
DM A CO RE
BUS 1
GP IO
P OR T
E
S P ORT2-3
DM A
E X TE R N A L
BUS 1
D MA CORE BUS 0
DMA
EXTERNAL
BUS 0
G PIO
P OR T
F
E X TE R N AL P OR T
FL A SH, S D R A M C ON T R OL
16
512kB OR 1M B
FLA SH M E M ORY
(A DS P -B F538F O NLY )
BOO T ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007
Analog Devices, Inc. All rights reserved.
ADSP-BF538/ADSP-BF538F
TABLE OF CONTENTS
Operating Conditions ........................................... 23
General Description ................................................. 3
Low Power Architecture ......................................... 3
System Integration ................................................ 3
ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 9
Real Time Clock ................................................... 9
Watchdog Timer ................................................ 10
Timers ............................................................. 10
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Ports ...................... 10
2-Wire Interface ................................................. 11
UART Ports ...................................................... 11
General-Purpose Ports ......................................... 11
Parallel Peripheral Interface ................................... 12
Controller Area Network (CAN) Interface ................ 13
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 14
Booting Modes ................................................... 16
Instruction Set Description ................................... 16
Development Tools ............................................. 17
Designing an Emulator Compatible Processor Board ... 18
Pin Descriptions .................................................... 19
Specifications ........................................................ 23
Electrical Characteristics ....................................... 24
Absolute Maximum Ratings ................................... 25
Package Information ............................................ 25
ESD Sensitivity ................................................... 25
Timing Specifications ........................................... 26
Clock and Reset Timing ..................................... 27
Asynchronous Memory Read Cycle Timing ............ 28
Asynchronous Memory Write Cycle Timing ........... 30
SDRAM Interface Timing .................................. 32
External Port Bus Request and Grant Cycle Timing .. 33
Parallel Peripheral Interface Timing ...................... 35
Serial Port Timing ............................................ 38
Serial Peripheral Interface Ports—Master Timing ..... 41
Serial Peripheral Interface Ports—Slave Timing ....... 42
General-Purpose Port Timing ............................. 43
Timer Cycle Timing .......................................... 44
JTAG Test And Emulation Port Timing ................. 45
Output Drive Currents ......................................... 46
Power Dissipation ............................................... 48
Test Conditions .................................................. 48
Thermal Characteristics ........................................ 51
316-Ball Mini-BGA Ball Assignments .......................... 52
Outline Dimensions ................................................ 55
Surface Mount Design .......................................... 56
Ordering Guide ..................................................... 56
REVISION HISTORY
05/07—Revision PrE to Rev.0
Add new wording to Power Savings section
Revise driver types in Pin Descriptions
Line changes in footnotes for Specifications and Operating
Conditions
Replace Rise and Fall Times graphs in Capacitive Loading
section
Reorder Ball Assignments
SPORT timing and External Late Frame Sync diagrams
changed.
Rev. 0 |
Page 2 of 56 |
May 2007
ADSP-BF538/ADSP-BF538F
GENERAL DESCRIPTION
The ADSP-BF538/ADSP-BF538F processors are members of
the Blackfin family of products, incorporating the Analog
Devices Inc./Intel Micro Signal Architecture (MSA). Blackfin
processors combine a dual-MAC state-of-the-art signal process-
ing engine, the advantages of a clean, orthogonal RISC-like
microprocessor instruction set, and single-instruction, multi-
ple-data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF538/ADSP-BF538F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in
Table 1.
Table 1. Processor Features
Feature
SPORTs
UARTs
SPI
TWI
PPI
CAN
Instruction SRAM
Data SRAM/Cache
Data SRAM
Scratchpad
Flash
Maximum Speed Grade
ADSP-
BF538
4
3
3
2
1
1
64K bytes
32K bytes
32K bytes
4K bytes
ADSP-
BF538F4
4
3
3
2
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
16-
ADSP-
BF538F8
4
3
3
2
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
512K
bit
16-
SYSTEM INTEGRATION
The ADSP-BF538/ADSP-BF538F processors are highly inte-
grated system-on-a-chip solutions for the next generation of
consumer and industrial applications including audio and video
signal processing. By combining advanced memory configura-
tions, such as on-chip flash memory, industry-standard
interfaces, and a high performance signal processing core, cost-
effective solutions can be quickly developed, without the need
for costly external components. The system peripherals include
three UART ports, three SPI ports, four serial ports (SPORTs),
one CAN interface, two 2-wire interfaces (TWI), four general-
purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface (PPI), and gen-
eral-purpose I/O pins.
ADSP-BF538/ADSP-BF538F PROCESSOR
PERIPHERALS
The ADSP-BF538/ADSP-BF538F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the block diagram
on Page 1).
The general-purpose peripherals include functions
such as UART, timers with PWM (pulse-width modulation)
and pulse measurement capability, general-purpose I/O pins, a
real time clock, and a watchdog timer. This set of functions sat-
isfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the device. In
addition to these general-purpose peripherals, the processors
contain high speed serial and parallel ports for interfacing to a
variety of audio, video, and modem codec functions. A CAN
2.0B controller is provided for automotive and industrial con-
trol networks. An interrupt controller manages interrupts from
the on-chip peripherals or from external sources. Power man-
agement control functions tailor the performance and power
characteristics of the processors and system to many application
scenarios.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real time clock, and timers, are supported by a flexible
DMA structure. There are also four separate memory DMA
channels dedicated to data transfers between the processor’s
various memory spaces, including external SDRAM and asyn-
chronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running with activity on all of the on-chip and external
peripherals.
The ADSP-BF538/ADSP-BF538F processors include an on-chip
voltage regulator in support of the processor’s dynamic power
management capability. The voltage regulator provides a range
of core voltage levels from a single 2.25 V to 3.6 V input. The
voltage regulator can be bypassed as needed.
Instruction SRAM/Cache 16K bytes
Not
256K
Applicable bit
533 MHz
1066
MMACS
BC-316
533 MHz
1066
MMACS
BC-316
533 MHz
1066
MMACS
BC-316
Package Option
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support and leading edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. They are designed using a low power and low
voltage methodology and feature dynamic power management
which is the ability to vary both the voltage and frequency of
operation to significantly lower overall power consumption.
Varying the voltage and frequency can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This translates into longer battery
life and lower heat dissipation.
Rev. 0 |
Page 3 of 56 |
May 2007
ADSP-BF538/ADSP-BF538F
BLACKFIN PROCESSOR CORE
As shown in
Figure 2 on Page 4,
the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). Quad 16-bit operations
are possible using the second ALU.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1
DA0
32
32
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
TO MEMORY
32
RAB
32
PREG
SD
LD1
LD0
32
32
32
32
32
ASTAT
SEQUENCER
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
16
8
8
8
16
8
DECODE
ALIGN
40
40
40
40
LOOP BUFFER
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. 0 |
Page 4 of 56 |
May 2007
ADSP-BF538/ADSP-BF538F
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
RESERVED
0xEF00 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE) OR
ON-CHIP FLASH (ADSP-BF538F ONLY)
0x2030 0000
0x2020 0000
ASYNC MEMORY BANK 2 (1M BYTE) OR
ON-CHIP FLASH (ADSP-BF538F ONLY)
ASYNC MEMORY BANK 1 (1M BYTE) OR
ON-CHIP FLASH (ADSP-BF538F ONLY)
0x2010 0000
0x2000 0000
0x0800 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
ASYNC MEMORY BANK 0 (1M BYTE) OR
ON -CHIP FLASH (ADSP-BF538F ONLY)
RESERVED
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
0xFFB0 0000
RESERVED
Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map
The memory DMA controllers provide high bandwidth data
movement capability. They can perform block transfers of code
or data between the internal memory and the external
memory spaces.
Internal (On-chip) Memory
The ADSP-BF538/ADSP-BF538F processors have three blocks
of on-chip memory providing high bandwidth access to
the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four way set-
associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both two-way set-associative cache and
SRAM functionality. This memory block is accessed at full pro-
cessor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
MEMORY ARCHITECTURE
The ADSP-BF538/ADSP-BF538F processors view memory as a
single unified 4G byte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/per-
formance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and perfor-
mance off-chip memory systems. See
Figure 3.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
Rev. 0 |
Page 5 of 56 |
May 2007
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