SAA128M4T27BV8FN-5B datasheet, PDF

Datasheet> All Categories > storage> storage> SAA128M4T27BV8FN-5B

SAA128M4T27BV8FN-5B: DescriptionDRAM; Categorystorage storage; File Size576KB，12 Pages; ManufacturerSPECTEK

Download Datasheet Parametric View All

SAA128M4T27BV8FN-5B Overview

DRAM

SAA128M4T27BV8FN-5B Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
Base Number Matches	1

Preview

Download Datasheet

View All

512Mb: x4, x8, x16

DDR SDRAM

DOUBLE DATA RATE

(DDR) SDRAM

FEATURES

•

PC2100, PC2700 and PC3200 compatible

•

VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V (For –6A & -

75A)

•

VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (For -5B)

•

Bi-directional data strobe (DQS) transmitted/ received with

data, i.e. source-synchronous data capture (x16 has two:

LDQS and UDQS – one per byte)

•

Internal, pipelined double-data-rate (DDR) architecture; two

data accesses per clock cycle

•

Differential clock inputs (CK and CK#)

•

Commands entered on each positive CK edge

•

DQS edge-aligned with data for READs; center-aligned

with data for WRITEs

•

DLL to align DQ and DQS transitions with CK

•

Four internal banks for concurrent operation

•

Data mask (DM) for masking write data (x16 has two: LDM

and UDM – one per byte)

•

Programmable burst lengths: 2, 4, or 8

•

Auto precharge option

•

Auto Refresh

•

Longer lead TSOP for improved reliability (OCPL)

•

2.5V I/O (SSTL_2 compatible)

•

These devices are optimized for single rank DIMM

applications

Package Types:

66-pin Plastic TSOP, OCPL

(400 mil width, 0.65mm pin pitch)

60-ball (10mm x 12.5mm) FBGA

Timing – Cycle Time:

5ns @ CL=3 (PC3200 or DDR400B)

6ns @ CL = 2.5 (PC2700 or DDR333)

7.5ns @ CL = 2.5 (PC2100 or DDR266)

Part number example:

(For part numbers prior to December

2004, refer to

page 12

for decoding.)

-5B

-6A

-75A

SAA64M8T27BV8TW-6A

PIN ASSIGNMENT (TOP VIEW)

66-PIN TSOP

Options:

Family:

SpecTek Memory

Configuration:

128 Meg x 4 (32 Meg x 4 x 4 banks)

64 Meg x 8 (16 Meg x 8 x 4 banks)

32 Meg x 16 (8 Meg x 16 x 4 banks)

Design ID:

DDR2 512 Megabit Design

(Call SpecTek Sales for details on

availability of “x” placeholders)

Voltage and refresh:

2.5V, Auto Refresh

2.5V, Self or Auto Refresh

Designation:

SAA

128M4

64M8

32M16

Tx7x

PDF=09005aef80c1b136 / Source=09005aef80c1a8c0

512Mb: x4, x8, x16 DDR SDRAM

Rev: 11/24/2004

www.spectek.com

SpecTek reserves the right to change products or specifications

without notice.

2003, 2004 SpecTek

Recommended Resources

Minimum system interface circuit based on AT89C52 microcontroller

Digital high resistance measurement circuit

YN5201 (electric fan) infrared remote control decoding circuit

16A gate transistor control circuit

M7120A surface grinder control circuit

Computer motherboard circuit diagram 440GX_32

The problem of open circuit at the input end of the same-phase amplifier circuit and output oscillation: [i=s]This post was last edited by CQU_ZMY on 2022-10-20 00:27[/i]Hey guys, I recently made a single-power-supply common-phase amplifier circuit, the circuit diagram is as follows. When the power suppl...; CQU_ZMY Analog electronics

Dear hardware engineers, can you solve differential equations?: Hardware engineers, do you know how to solve differential equations? When I just graduated and was looking for a job, I was interviewed by a company as a hardware engineer. Among the interview questio...; lingking Integrated technical exchanges

Temperature Problem Solved for You (V) Efficient Cold Chain Management through Scalable Temperature Sensors: In previous articles, we have introduced the basic principles of temperature sensors. In order to preserve nutrients and ensure quality and product safety, manufacturers specify the transportation and...; EEWORLD社区 TI Technology Forum

Field Programmable Gate Array is...? ?: When I talk to people about FPGAs , I hear a lot of people say, " I don't know how they work , " " They're too complicated , " and " I can't program them in C. " I hate to see such an amazing device g...; mdy-吴伟杰 FPGA/CPLD

High-pass filter, low-pass filter, band-pass filter, band-stop filter, detector and frequency selection: High-pass filter, low-pass filter, band-pass filter, band-stop filter, detector and frequency selection1. These filters require op amp + capacitor to be implemented. Are there any integrated filter ch...; QWE4562009 Discrete Device

Zero-based temperature and humidity monitoring host computer: [i=s]This post was last edited by Fillmore on 2020-7-31 18:29[/i]PrefaceMany netizens asked me what language is good for writing a host computer. C#, C++, Python, etc. can all be used, but you must le...; Fillmore Real-time operating system RTOS

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components