M29F040B
4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory
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SINGLE 5V ± 10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 45ns
PROGRAMMING TIME
– 8 µs per Byte typical
8 UNIFORM 64 Kbytes MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
PLCC32 (K)
TSOP32 (N)
8 x 20mm
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ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
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UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E2h
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ECOPACK
®
PACKAGES AVAILABLE
September 2005
1/20
M29F040B
Figure 1. Logic Diagram
Table 1. Signal Names
A0-A18
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
VCC
DQ0-DQ7
E
19
A0-A18
8
DQ0-DQ7
G
W
V
CC
W
E
G
M29F040B
V
SS
VSS
AI02900
Figure 2. PLCC Connections
Figure 3. TSOP Connections
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M29F040B
25
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02901
A11
A9
A8
A13
A14
A17
W
VCC
A18
A16
A15
A12
A7
A6
A5
A4
A12
A15
A16
A18
VCC
W
A17
1
32
8
9
M29F040B
25
24
16
17
AI02902
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
2/20
M29F040B
Table 2. Absolute Maximum Ratings
(1)
Symbol
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
T
A
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–40 to 85
–40 to 125
–50 to 125
–65 to 150
–0.6 to 6
–0.6 to 6
–0.6 to 13.5
Unit
°C
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
SUMMARY DESCRIPTION
The M29F040B is a 4 Mbit (512Kb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM. The
M29F040B is fully backward compatible with the
M29F040.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory
by taking care of all of the special operations that
are required to update the memory contents. The
end of a program or erase operation can be de-
tected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 20mm),
and PLCC32 packages. It is supplied with all the
bits erased (set to ‘1’).
In order to meet environmental requirements, ST
offers the M29F040B in ECOPACK
®
packages.
ECOPACK packages are Lead-free. The category
of second Level Interconnect is marked on the
package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum rat-
ings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Table 3. Uniform Block Addresses, M29F040B
#
7
6
5
4
3
2
1
0
Size
(Kbytes)
64
64
64
64
64
64
64
64
Address Range
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
3/20
M29F040B
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at V
IH
the Supply Current is
reduced to the TTL Standby Supply Current, I
CC2
.
To further reduce the Supply Current to the CMOS
Standby Supply Current, I
CC3
, Chip Enable should
be held within V
CC
± 0.2V. For Standby current
levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC4
, for Program or Erase operations un-
til the operation completes.
4/20
M29F040B
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the CMOS Standby Supply Current, I
CC3
.
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Table 4. Bus Operations
Operation
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Note: X = V
IL
or V
IH
.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection
and
Blocks Unprotection.
Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed. Block
Protection and Blocks Unprotection operations
must only be performed on programming equip-
ment. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
E
V
IL
V
IL
X
V
IH
V
IL
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
V
IH
Address Inputs
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Data
Inputs/Outputs
Data Output
Data Input
Hi-Z
Hi-Z
20h
E2h
5/20
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