S70PL254J
256 Megabit (16 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Same-die Stack Flash Memory
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
Two 128 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Dual Chip Enable inputs
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
SecSi
TM
(Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
PRELIMINARY
SOFTWARE FEATURES
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV, Am29DL,
and AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
WP#/ ACC (Write Protect/Acceleration) input
— At V
IL
, hardware level protection for the first and last
two 4K word sectors.
— At V
IH
, allows removal of sector protection
— At V
HH
, provides accelerated programming in a factory
setting
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Package options
— MCP-compatible pinout
8 x 11.6 mm, 84-ball Fine-pitch BGA
Compatible with MCP pinout, allowing easy
integration of RAM into existing designs
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 60 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
Publication Number
S70PL254J
Revision
A
Amendment
1
Issue Date
May 21, 2004
P R E L I M I N A R Y
General Description
The S70PL254J00 consists of two S29PL127J flash memory devices. The PL127J
is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash mem-
ory device organized as 8 Mwords. The devices are offered in the following
package:
8mm x 11.6mm, 84-ball Fine pitch BGA multi-chip compatible
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V V
PP
is not
required for write or erase operations.
The device offers fast page access times of 25 to 30 ns, with corresponding ran-
dom access times of 60 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Bank
A
B
C
D
Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 sin-
gle-power-supply Flash standard.
Commands are written to the command
register using standard microprocessor write timing. Register contents serve as
inputs to an internal state-machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and data needed for the
2
S70PL254J
S70PL254JA1 May 21, 2004
P R E L I M I N A R Y
programming and erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four. Device erasure occurs by executing
the erase command sequence.
The host system can detect whether a program or erase operation is complete by
reading the DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume
feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved. If a read
is needed from the SecSi Sector area (One Time Program area) after an erase
suspend, then the user must use the proper command sequence to enter and exit
this region.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the standby mode. Power consumption
is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
May 21, 2004 S70PL254JA1
S70PL254J
3
P R E L I M I N A R Y
Table of Contents
S70PL254J 1
General Description 2
Simultaneous Read/Write Operation with Zero Latency ......... 2
Page Mode Features ............................................................................... 2
Standard Flash Memory Features ...................................................... 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .6
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Simultaneous Read/Write Block Diagram . . . . . . 8
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .9
84-Ball Fine-pitch BGA—MCP Compatible ................................... 9
Special Package Handling Instructions .............................................10
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 11
MCP Look-Ahead Connection Diagram-For Reference Only . 11
Special Package Handling Instructions ............................................. 12
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 14
Table 1. Device Bus Operations ...........................................14
Persistent Protection Bit Lock ..........................................................33
High Voltage Sector Protection ........................................................33
Figure 1. In-System Sector Protection/Sector Unprotection Algo-
rithms ............................................................................. 34
Temporary Sector Unprotect ...........................................................35
Figure 2. Temporary Sector Unprotect Operation................... 35
SecSi™ (Secured Silicon) Sector Flash Memory Region .............35
Factory-Locked Area (64 words) .....................................................35
Customer-Lockable Area (64 words) ............................................ 36
SecSi Sector Protection Bits .............................................................. 36
Figure 3. SecSi Sector Protect Verify.................................... 37
Hardware Data Protection .................................................................37
Low VCC Write Inhibit .......................................................................37
Write Pulse “Glitch” Protection .......................................................37
Logical Inhibit ..........................................................................................37
Power-Up Write Inhibit ......................................................................37
Common Flash Memory Interface (CFI). . . . . . . 38
Table
Table
Table
Table
9. CFI Query Identification String ..............................
10. System Interface String ......................................
11. Device Geometry Definition .................................
12. Primary Vendor-Specific Extended Query ...............
38
39
39
39
Requirements for Reading Array Data ........................................... 14
Random Read (Non-Page Read) ....................................................... 14
Page Mode Read ..................................................................................... 15
Table 2. Page Select ..........................................................15
Simultaneous Read/Write Operation .............................................. 15
Table 3. Bank Select .........................................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 41
Reading Array Data .............................................................................. 41
Reset Command .................................................................................... 41
Autoselect Command Sequence ...................................................... 42
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .. 42
Word Program Command Sequence ............................................. 42
Unlock Bypass Command Sequence ............................................... 43
Figure 4. Program Operation .............................................. 44
Writing Commands/Command Sequences ................................... 16
Accelerated Program Operation ...................................................... 16
Autoselect Functions ............................................................................ 16
Standby Mode ..........................................................................................16
Automatic Sleep Mode ......................................................................... 17
RESET#: Hardware Reset Pin ............................................................ 17
Output Disable Mode ........................................................................... 17
Table 4. Sector Architecture ...............................................18
Table 5. SecSiTM Sector Addresses .....................................25
Chip Erase Command Sequence ...................................................... 44
Sector Erase Command Sequence .................................................. 44
Figure 5. Erase Operation .................................................. 45
Erase Suspend/Erase Resume Commands .................................... 46
Command Definitions Tables ...........................................................48
Table 13. Memory Array Command Definitions ..................... 48
Table 14. Sector Protection Command Definitions ................. 49
Write Operation Status . . . . . . . . . . . . . . . . . . . . 50
DQ7: Data# Polling .............................................................................. 50
Figure 6. Data# Polling Algorithm ....................................... 51
Autoselect Mode .................................................................................. 25
Table 6. Autoselect Codes (High Voltage Method) ..................26
Table 7. Boot Sector/Sector Block Addresses for Protection/Unpro-
tection ............................................................................27
RY/BY#: Ready/Busy# .......................................................................... 51
DQ6: Toggle Bit I ................................................................................... 51
Figure 7. Toggle Bit Algorithm ............................................ 52
Selecting a Sector Protection Mode ...............................................28
Table 8. Sector Protection Schemes .....................................28
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 28
Persistent Sector Protection .............................................................28
Password Sector Protection .............................................................28
WP# Hardware Protection ...............................................................28
Selecting a Sector Protection Mode ...............................................28
Persistent Sector Protection . . . . . . . . . . . . . . . . 29
Persistent Protection Bit (PPB) ........................................................ 29
Persistent Protection Bit Lock (PPB Lock) ................................... 29
Persistent Sector Protection Mode Locking Bit ........................... 31
Password Protection Mode. . . . . . . . . . . . . . . . . . 31
Password and Password Mode Locking Bit .................................. 32
64-bit Password ..................................................................................... 32
Write Protect (WP#) .......................................................................... 32
4
DQ2: Toggle Bit II ................................................................................ 52
Reading Toggle Bits DQ6/DQ2 .........................................................53
DQ5: Exceeded Timing Limits ...........................................................53
DQ3: Sector Erase Timer ...................................................................53
Table 15. Write Operation Status ....................................... 54
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 55
Figure 8. Maximum Overshoot Waveforms............................ 55
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Wireless (W) Devices ......................................................................... 56
Industrial (I) Devices ............................................................................ 56
Extended (E) Devices .......................................................................... 56
Supply Voltages ...................................................................................... 56
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 16. CMOS Compatible .............................................. 57
Test Conditions ..................................................................................... 58
Figure 9. Test Setups ....................................................... 58
S70PL254J
S70PL254JA1 May 21, 2004
P R E L I M I N A R Y
Table 17. Test Specifications ..............................................58
Switching Waveforms .......................................................................... 58
Table 18. Key to Switching Waveforms ................................58
Figure 10. Input Waveforms and Measurement Levels............ 59
Figure 19. Toggle Bit Timings (During Embedded Algorithms) . 66
Figure 20. DQ2 vs. DQ6 ..................................................... 67
Protect/Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 22. Temporary Sector Unprotect ................................ 67
Figure 21. Temporary Sector Unprotect Timing Diagram......... 67
Figure 22. Sector/Sector Block Protect and Unprotect Timing Dia-
gram............................................................................... 68
V
CC
RampRate ....................................................................................... 59
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .60
Read Operations ...................................................................................60
Table 19. Read-Only Operations ..........................................60
Figure 11. Read Operation Timings...................................... 60
Figure 12. Page Read Operation Timings .............................. 61
Controlled Erase Operations ...........................................................68
Table 23. Alternate CE# Controlled Erase and Program Operations
68
Table 24. Alternate CE# Controlled Write (Erase/Program) Opera-
tion Timings .................................................................... 69
Figure 23. Timing Diagram for Alternating Between CE1# and
CE2# Control ................................................................... 69
Table 25. Erase And Programming Performance ................... 70
Reset .......................................................................................................... 61
Table 20. Hardware Reset (RESET#) ...................................61
Figure 13. Reset Timings ................................................... 62
Erase/Program Operations ................................................................ 63
Table 21. Erase and Program Operations ..............................63
Timing Diagrams ................................................................................... 64
Figure
Figure
Figure
Figure
Figure
66
14. Program Operation Timings................................. 64
15. Accelerated Program Timing Diagram ................... 64
16. Chip/Sector Erase Operation Timings.................... 65
17. Back-to-back Read/Write Cycle Timings ................ 65
18. Data# Polling Timings (During Embedded Algorithms)
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 70
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 71
TSB084—84-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package
71
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 72
May 21, 2004 S70PL254JA1
S70PL254J
5
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