DDR SDRAM (Rev.1.0)
Jul. '01
Preliminary
M2S56D20/ 30/ 40AKT
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit,
M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit,
M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40AKT achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
-75A
-75
-10
Clock Rate
CL=2 *
133MHz
100MHz
100MHz
CL=2.5 *
133MHz
133MHz
125MHz
* CL = CAS(Read) Latency
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.1.0)
Jul. '01
Preliminary
M2S56D20/ 30/ 40AKT
PIN CONFIGURATION(TOP VIEW)
X4
X8
X 16
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
VSS
DQ7
NC
VSSQ VSSQ
NC
NC
DQ6
DQ3
VDDQ VDDQ
NC
NC
DQ5
NC
VSSQ VSSQ
NC
NC
DQ4
DQ2
VDDQ VDDQ
NC
NC
VSSQ VSSQ
DQS
DQS
NC
NC
VREF VREF
VSS
VSS
DM
DM
/CLK /CLK
CLK
CLK
CKE
CKE
NC
NC
A12
A12
A11
A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS
VSS
64pin STSOP
PIN PITCH 0.4 mm
CLK,/CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-7
DQS
DM
Vref
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Data Strobe
: Write Mask
: Reference Voltage
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2
DDR SDRAM (Rev.1.0)
Jul. '01
Preliminary
M2S56D20/ 30/ 40AKT
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-12
Input
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input
Input / Output
DQS
Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
DM
Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
MITSUBISHI ELECTRIC
3
DDR SDRAM (Rev.1.0)
Jul. '01
Preliminary
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
BLOCK DIAGRAM
DLL
DQ0 - 15
UDQS,LDQS
I/O Buffer
QS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
Clock Buffer
A 0-12
BA0,1
C L K /C L K C K E
/CS
Control Signal Buffer
/RAS /CAS
/ WE
UDM,
LDM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 S 56 D 3 0 A TP –75A
Speed Grade
10: 125 MHz@CL=2.5,100MHz@CL=2.0
75:
133 MHz@CL=2.5,100MHz@CL=2.0
75 A: 133MHz@CL=2.5,133MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
n
Organization 2
2: x4, 3: x8, 4: x16
D DR Synchronous DRAM
Density 56: 256M bits
Interface
V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
4
DDR SDRAM (Rev.1.0)
Jul. '01
Preliminary
MITSUBISHI LSIs
M2S56D20/ 30/ 40AKT
256 M D o u b l e D a t a R a t e S y n c h r o n o u s D R A M
BASIC FUNCTIONS
The M2S56D20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,
READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This co mmand also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA
).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
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