REI Datasheet
TLC32044C, ‘32044E, ‘32044I, ‘32044M, ‘32045C, ‘32045I
Voice-Band Analog Interface Circuits
The TLC32044 and TLC32045 are complete analog-to-digital and digital-to-analog input and output
systems on single monolithic CMOS chips. The TLC32044 and TLC32045 integrate a bandpass
switched-capacitor antialiasing input filter, a 14-bit-resolution A/D converter, four microprocessor-
compatible serial port modes, a 14-bit-resolution D/A converter, and a low-pass switched-capacitor
output-reconstruction filter. The devices offer numerous combinations of master clock input
frequencies and conversion/sampling rates, which can be changed via digital processor control.
Rochester Electronics
Manufactured Components
Rochester branded components are
manufactured using either die/wafers
purchased from the original suppliers
or Rochester wafers recreated from the
original IP. All recreations are done with
the approval of the OCM.
Parts are tested using original factory
test programs or Rochester developed
test solutions to guarantee product
meets or exceeds the OCM data sheet.
Quality Overview
• ISO-9001
• AS9120 certification
• Qualified Manufacturers List (QML) MIL-PRF-38535
•
Class Q Military
• Class V Space Level
• Qualified Suppliers List of Distributors (QSLD)
• Rochester is a critical supplier to DLA and
meets all industry and DLA standards.
Rochester Electronics, LLC is committed to supplying
products that satisfy customer expectations for
quality and are equal to those originally supplied by
industry manufacturers.
The original manufacturer’s datasheet accompanying this document reflects the performance
and specifications of the Rochester manufactured version of this device. Rochester Electronics
guarantees the performance of its semiconductor products to the original OEM specifications.
‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be
based on product characterization, design, simulation, or sample testing.
© 2013 Rochester Electronics, LLC. All Rights Reserved 08272013
To learn more, please visit
www.rocelec.com
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
D
D
D
D
D
D
D
D
description
The TLC32044 and TLC32045 are complete
analog-to-digital and digital-to-analog input and
output systems on single monolithic CMOS chips.
The TLC32044 and TLC32045 integrate a
bandpass switched-capacitor antialiasing input
filter, a 14-bit-resolution A/D converter, four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter.
The devices offer numerous combinations of
master clock input frequencies and conversion/
sampling rates, which can be changed via digital
processor control.
DR
MSTR CLK
V
DD
REF
DGTL GND
SHIFT CLK
EODX
FSR
EODR
RESET
NU
NU
NU
IN +
5
6
7
8
9
10
4
3 2
1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
D
14-Bit Dynamic Range ADC and DAC
2’s Complement Format
Variable ADC and DAC Sampling Rate Up
to 19,200 Samples per Second
Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter
Serial Port for Direct Interface to
TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25,
and TMS320C30 Digital Signal Processors
Synchronous or Asynchronous ADC and
DAC Conversion Rates With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments
Serial Port Interface to SN74(54)299
Serial-to-Parallel Shift Register for Parallel
Interface to TMS(SMJ)32010,
TMS(SMJ)320C15, or Other Digital
Processors
Internal Reference for Normal Operation
and External Purposes, or Can Be
Overridden by External Reference
CMOS Technology
J† OR N PACKAGE
(TOP VIEW)
NU
RESET
EODR
FSR
DR
MSTR CLK
V
DD
REF
DGTL GND
SHIFT CLK
EODX
DX
WORD/BYTE
FSX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NU
NU
IN +
IN –
AUX IN +
AUX IN –
OUT +
OUT –
V
CC +
V
CC –
ANLG GND
ANLG GND
NU
NU
† Refer to the mechanical data for the JT package.
FK OR FN PACKAGE
(TOP VIEW)
IN –
AUX IN +
AUX IN –
OUT +
OUT –
V
CC +
V
CC –
NU – Nonusable; no external connection should be made to
these terminals (see Table 2).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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DX
WORD/BYTE
FSX
NU
NU
ANLG GND
ANLG GND
1
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC CHIP
CARRIER
(FN)
TLC32044CFN
TLC32045CFN
TLC32044EFN
TLC32044IN
TLC32045IN
TLC32044MJ
TLC32044MFK
PLASTIC DIP
(N)
TLC32044CN
TLC32045CN
CERAMIC DIP
(J)
CHIP CARRIER
(FK)
0°C to 70°C
– 20°C to 85°C
– 40°C to 85°C
– 55°C to 125°C
description (continued)
Typical applications for the TLC32044 and TLC32045 include speech encryption for digital transmission,
speech recognition/ storage systems, speech synthesis, modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling
rate), analog interface for digital signal processors (DSPs), industrial process control, biomedical
instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation
recorders. Four serial modes, which allow direct interface to the TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25, and TMS(SMJ)320C30 digital signal processors, are provided. Also, when the transmit and
receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two
SN74(54)299 serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in
parallel to the TMS(SMJ)32010, TMS(SMJ)320C15, and other digital signal processors, or external FIFO
circuitry. Output data pulses are emitted to inform the processor that data transmission is complete or to allow
the DSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the
functions of the TLC32044 or TLC32045 can be selected and adjusted coincidentally with signal processing via
software control.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively. The input filter is implemented in switched-capacitor technology
and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data
filtering. When only low-pass filtering is desired, the high-pass filter can be switched out of the signal path. A
selectable, auxiliary, differential analog input is provided for applications where more than one analog input is
required.
The A/D and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference
is provided to ease the design task and to provide complete control over the performance of the TLC32044 or
TLC32045. The internal voltage reference is brought out to a terminal and is available to the designer. Separate
analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic
range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum.
The only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x) / x correction filter and is implemented in switched-capacitor technology. This
filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal. The on-board
(sin x) / x correction filter can be switched out of the signal path using digital signal processor control, if desired.
The TLC32044C and TLC32045C are characterized for operation from 0°C to 70°C. The TLC32044E is
characterized for operation from – 20°C to 85°C. The TLC32044I and TLC32045I are characterized for
operation from – 40°C to 85°C. The TLC32044M is characterized for operation from – 55°C to 125°C.
2
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TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
functional block diagram
IN +
IN –
AUX IN +
AUX IN –
Receive Section
M
U
X
Filter
M
U
X
SERIAL
PORT
FSR
DR
EODR
MSTER CLK
Internal
Voltage
Reference
Filter
OUT +
OUT –
M
U
X
sin x/x
Correction
SHIFT CLK
WORD/BYTE
DX
FSX
D/A
EODX
A/D
Transmit Section
VCC + VCC – ANLG DTGL VDD
GND GND (Digital)
REF
RESET
Terminal Functions
TERMINAL
NAME
ANLG GND
AUX IN +
NO.
17,18
24
I
I/O
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
Noninverting auxiliary analog input stage. AUX IN + can be switched into the bandpass filter and A/D
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
t
th i
ft
t l th
i t
i th
t l
i t i
1 th
ili
i
t
will replace the IN + and IN – inputs. If the bit is a 0, the IN + and IN – inputs will be used (see the AIC DX
re lace
in uts.
in uts
data word format section).
Inverting auxiliary analog input (see the above AUX IN + description).
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
O
Data receive. DR is used to transmit the ADC output bits from the AIC to the TMS320 (SMJ320) serial port.
This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT
CLK signal.
Data transmit. DX is used to receive the DAC input bits and timing and control information from the TMS320
(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with
the SHIFT CLK signal.
End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information
have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt
a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port
and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to
differentiate between the two bytes as to which is first and which is second. EODR does not occur after
secondary communication.
AUX IN –
DGTL GND
DR
23
9
5
I
DX
12
I
EODR
3
O
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3
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
EODX
NO.
11
I/O
O
DESCRIPTION
End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is
second.
Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after
secondary communications.
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
y
g
,
(
)
g
g
AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
Noninverting input to analog input amplifier stage
Inverting input to analog input amplifier stage
Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal
Timing Configuration diagram).
Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
Inverting output of analog output power amplifier. OUT– is functionally identical with and complementary
to OUT +.
Internal voltage reference. An internal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.
Reset function. RESET is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-khz
data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’
and RA’, are reset to 1. The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1.
This initialization allows normal serial-port communication to occur between the AIC and DSP.
Shift clock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port Timing and Internal Timing Configuration diagrams).
Digital supply voltage, 5 V
±
5%
Positive analog supply voltage, 5 V
±
5%
Negative analog supply voltage, – 5 V
±
5%
FSR
4
O
FSX
14
O
IN +
IN –
MSTR CLK
26
25
6
I
I
I
OUT +
OUT –
REF
RESET
22
21
8
2
O
O
I/O
I
SHIFT CLK
10
O
VDD
VCC +
VCC –
7
20
19
4
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