Q22F4GPXXG24ALT datasheet, PDF

Q22F4GPXXG24ALT: DescriptionSingle Color LED, Green, Diffused, 22mm, PLASTIC PACKAGE-4; CategoryLED optoelectronic/LED photoelectric; File Size2MB，3 Pages; ManufacturerAPEM; Environmental Compliance

Download Datasheet Parametric View All

Q22F4GPXXG24ALT Overview

Single Color LED, Green, Diffused, 22mm, PLASTIC PACKAGE-4

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	PLASTIC PACKAGE-4
Reach Compliance Code	compliant
Other features	UL RECOGNIZED
color	GREEN
Configuration	SINGLE
Lens type	DIFFUSED
Nominal luminous intensity	70.0 mcd
Installation features	PANEL MOUNT
Number of functions	1
Number of terminals	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Optoelectronic device types	SINGLE COLOR LED
total height	2.5 mm
method of packing	BULK
shape	CYLINDRICAL
size	22 mm
surface mount	NO
perspective	100 deg
Base Number Matches	1

04681 Q-Series blue IFC.indd 19

13/12/07 15:16:24

【Xianji HPM6750 Review】Interim (Final) Summary: Time flies. It has been two months since I received the board. A few days ago, the administrator said that the progress will be finished on June 30. I was surprised that it was so fast. It felt like t...; littleshrimp Domestic Chip Exchange

Shortlist | 2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition: [Competition Details] 2020-2021 ON Semiconductor and Avnet IoT Creative Design CompetitionThank you very much for your support of this competition!The finalists were selected by ON Semiconductor, Avne...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

FPGA_100 Days Journey_Key Debounce.pdf: FPGA_100 Days Journey_Key Debounce.pdf...; zxopenljx EE_FPGA Learning Park

CSM Code Security Module FAQ: Naming convention -- CSM: Code Security Module Code Security Module -- ECSL: Emulation Code Security Logic Emulation Code Security LogicFrequently asked questions Q: What happens when the CSM automati...; Jacktang Microcontroller MCU

FPGA implementation of DVI output image selection interception.pdf: FPGA implementation of DVI output image selection interception.pdf...; zxopenljx EE_FPGA Learning Park

ASIC Design-FPGA Prototype Verification: ASIC Design-FPGA Prototype Verification...; 雷北城 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components