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MC74AC109DT

Description
Dual JK Positive Edge−Triggered Flip−Flop
Categorylogic    logic   
File Size231KB,9 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric View All

MC74AC109DT Overview

Dual JK Positive Edge−Triggered Flip−Flop

MC74AC109DT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Reach Compliance Code_compli
seriesAC
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-KBAR FLIP-FLOP
Maximum Frequency@Nom-Su100000000 Hz
MaximumI(ol)0.012 A
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingRAIL
Peak Reflow Temperature (Celsius)235
power supply3.3/5 V
propagation delay (tpd)16 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax125 MHz
MC74AC109, MC74ACT109
Dual JK Positive
Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high−speed
completely independent transition clocked JK flip−flops. The clocking
operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs
together.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
http://onsemi.com
16
1
DIP−16
N SUFFIX
CASE 648
Outputs Source/Sink 24 mA
′ACT109
Has TTL Compatible Inputs
V
CC
16
C
D2
15
C
D
16
Q
2
10
Q
Q
J
2
14
J
K
2
13
K
CP
2
12
CP
S
D2
11
S
D
Q
2
9
16
1
SO−16
D SUFFIX
CASE 751B
1
TSSOP−16
DT SUFFIX
CASE 948F
C
D1
J
1
K
1
CP
1
S
D1
Q
1
Q
1
1
C
D1
2
J
1
3
K
1
4
CP
1
5
S
D1
6
Q
1
7
Q
1
8
GND
16
1
EIAJ−16
M SUFFIX
CASE 966
Figure 1. Pinout; 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
,
Q
2
FUNCTION
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
ORDERING INFORMATION
Device
MC74AC109N
MC74ACT109N
MC74AC109D
MC74ACT109D
MC74AC109DR2
MC74ACT109DR2
MC74AC109DT
MC74ACT109DT
MC74AC109DTR2
Package
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
SOIC−16
TSSOP−16
TSSOP−16
Shipping
25 Units/Rail
25 Units/Rail
48 Units/Rail
48 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units/Rail
96 Units/Rail
TSSOP−16 2500 Tape & Reel
MC74ACT109DTR2 TSSOP−16 2500 Tape & Reel
MC74AC109M
MC74ACT109M
MC74AC109MEL
MC74ACT109MEL
EIAJ−16
EIAJ−16
EIAJ−16
EIAJ−16
50 Units/Rail
50 Units/Rail
2000 Tape & Reel
2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
Rev. 6
1
Publication Order Number:
MC74AC109/D
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