®
FAST CMOS
PARITY BUS
TRANSCEIVER
DESCRIPTION:
IDT54/74FCT833A
IDT54/74FCT833B
Integrated Device Technology, Inc.
FEATURES:
• Equivalent to AMD’s Am29833 bipolar parity bus
transceiver in pinout/function, speed and output drive
over full temperature and voltage supply extremes
• High-speed bidirectional bus transceiver for processor-
organized devices
• IDT54/74FCT833A equivalent to Am29833A speed and
output drive
• IDT54/74FCT833B 30% faster than Am29833A
• Buffered direction and three-state controls
• Error flag with open-drain output
• I
OL
= 48mA (commercial) and 32mA (military)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Available in plastic DIP, CERDIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT833s are high-performance bus
transceivers designed for two-way communications. They
each contain an 8-bit data path from the R (port) to the T (port),
an 8-bit data path from the T (port) to the R (port), and a 9-bit
parity checker/generator. The error flag can be clocked and
stored in a register and read at the
ERR
output. The clear
(
CLR
) input is used to clear the error flag register.
The output enables
OE
T
and
OE
R
are used to force the
port outputs to the high-impedance state so that the device
can drive bus lines directly. In addition,
OE
R
and
OE
T
can be
used to force a parity error by enabling both lines
simultaneously. This transmission of inverted parity gives the
designer more system diagnostic capability. The devices are
specified at 48mA and 32mA output sink current over the
commercial and military temperature ranges, respectively.
FUNCTIONAL BLOCK DIAGRAM
R
I
8
8
T
I
PARITY
OE
T
OE
R
8
8
S
MUX
9
9-BIT
PARITY TREE
D
P
CLK
CP
CLR
2557 drw 01
Q
Q
ERR
CLR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4621/2
7.21
1
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
R
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
ERR
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
P24-1,
D24-1,
S024-2
&
E24-1
21
20
19
18
17
16
15
14
13
ERR
CLR
GND
NC
CLK
OE
T
PARITY
Vcc
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
PARITY
OE
T
CLK
INDEX
R
2
R
3
R
4
NC
R
5
R
6
R
7
R
1
R
0
OE
R
NC
Vcc
T
0
T
1
4
5
6
7
8
9
10
3 2
1
28 27 26
25
24
23
22
21
20
L28-1
11
19
12 13 14 15 16 17 18
T
2
T
3
T
4
NC
T
5
T
6
T
7
2557 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
I/O
I
I/O
O
Description
RECEIVE enable input.
8-bit RECEIVE data input/output.
Output from fault registers. Register
detection of odd parity fault on rising clock
edge (CLK). A registered
ERR
output
remains LOW until cleared. Open drain
output, requires pull up resistor.
Clears the fault register output.
8-bit TRANSMIT data input/output.
1-bit PARITY output.
TRANSMIT enable input.
External clock pulse input for fault register
flag.
2557 tbl 01
ERROR FLAG OUTPUT FUNCTION TABLE
(1,2)
OE
R
R
I
CLR
H
H
H
L
Inputs
CLK
↑
↑
↑
—
Internal
Output
To Device Pre-State
Point “P”
H
—
L
—
ERR
n–1
H
L
—
—
Output
ERR
H
L
L
H
Function
Sample
(1’s
Capture)
Clear
2557 tbl 02
ERR
CLR
T
I
PARITY
I
I/O
I/O
I
I
OE
T
CLK
NOTES:
1.
OE
T
is HIGH and
OE
R
is LOW.
2. H = HIGH
L = LOW
↑
= LOW-to-HIGH transition of clock
– = Don't Care or Irrelevant
7.21
2
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
(2)
Inputs
Outputs
T
I
Incl Parity
CLK
↑
↑
↑
↑
↑
↑
↑
↑
—
H or L
—
↑
↑
↑
↑
↑
↑
R
I
(∑ or H’s)
H (Odd)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
—
—
—
H or L (Odd)
H or L (Even)
H (Odd)
H (Even)
L (Odd)
L (Even)
(∑ of H’s)
NA
NA
NA
NA
H (Odd)
H (Even)
L (Odd)
L (Even)
—
—
—
—
—
NA
NA
NA
NA
R
I
NA
NA
NA
NA
H
H
L
L
NA
Z
Z
Z
Z
NA
NA
NA
NA
T
I
H
H
L
L
NA
NA
NA
NA
NA
Z
Z
Z
Z
H
H
L
L
Parity
L
H
L
H
NA
NA
NA
NA
NA
Z
Z
Z
Z
H
L
H
L
OE
T
L
L
L
L
H
H
H
H
—
H
H
H
H
L
L
L
L
OE
R
H
H
H
H
L
L
L
L
—
H
H
H
H
L
L
L
L
CLR
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
ERR
(1)
H
L
H
L
H
L
H
L
H
*
H
H
L
L
H
L
H
Function
Transmit data from R Port
to T Port with parity;
receiving path is disabled.
Receive data from T Port
to R Port with parity test
resulting in flag:
transmitting path is disabled.
Clear the state of error flag
register.
Both transmitting and
receiving paths are disabled.
Parity logic defaults to
transmit mode.
Forced-error checking.
NOTES:
1. Output state assumes HIGH output pre-state.
2. H
= HIGH
L
= LOW
↑
= LOW-to-HIGH transition of clock
*No change to stored Error State
2557 tbl 03
Z =
NA =
– =
High Impedance
Not Applicable
Don’t Care or Irrelevant
Odd =
Even =
I
=
Odd number of logic one’s
Even number of logic one’s
0, 1, 2, 3, 4, 5, 6, 7
7.21
3
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
Rating
Terminal Voltage
with Respect
to GND
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol Parameter
(1)
C
IN
C
I/O
Input
Capacitance
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
tbl 05
V
TERM(3)
–0.5 to V
CC
–0.5 to V
CC
V
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
NOTE:
2557
1. This parameter is guaranteed by characterization but not tested.
NOTES:
2557 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Inputs and V
CC
terminals.
3. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O Pins)
Input LOW Current
(Except I/O Pins)
Input HIGH Current
(I/O Pins Only)
Input LOW Current
(I/O Pins Only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
(Except
ERR
)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
=V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
Vcc = Min., I
N
= –18mA
Vcc = Max.
(3)
, V
O
= GND
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
Vcc = Min.
I
OH
= –300µA
I
OH
= –15mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –24mA COM’L.
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
Vcc = Min.
Except
I
OL
= 300µA
V
IN
= V
IH
ERR
I
OL
= 32 mA MIL.
I
OL
= 48mA COM’L.
or V
IL
ERR
I
OL
= 48mA
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
2.4
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
15
15
(4)
–15
(4)
–15
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
0.5
Unit
V
V
µA
µA
V
mA
V
V
OL
Output LOW Voltage
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
2557 tbl 06
7.21
4
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Outputs Open
Test Conditions
(1)
Vcc = Max.; V
IN
≥
V
HC
, V
IN
≤
V
LC
Vcc = Max.
V
IN
= 3.4V
(3)
Vcc = Max.
V
IN
≥
V
HC
V
IN
≤
V
LC
OE
T
=
OE
R
= GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
V
IN
≥
V
HC
Outputs Open
V
IN
≤
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
OE
T
= GND
V
IN
= 3.4V
OE
R
= V
CC
V
IN
= GND
f
i
= 2.5MHz
One Bit Toggling
Vcc = Max.
V
IN
≥
V
HC
Outputs Open
V
IN
≤
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
OE
T
= GND
V
IN
= 3.4V
f
i
= 2.5MHz
V
IN
= GND
OE
R
= V
CC
Eight Bits Toggling
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
—
1.4
3.4
mA
—
1.9
5.4
—
4.0
7.8
(5)
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2557 tbl 07
7.21
5
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