HMP112P7EFR4C-S5 datasheet, PDF

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HMP112P7EFR4C-S5: DescriptionDDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size401KB，26 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HMP112P7EFR4C-S5 Overview

DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

HMP112P7EFR4C-S5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
JESD-30 code	R-PBGA-B60
length	133.35 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM MODULE
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	55 °C
Minimum operating temperature
organize	128MX8
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	30 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	2.7 mm
Base Number Matches	1

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240pin Registered DDR2 SDRAM DIMMs based on 1Gb version E

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb

version E based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width

form factor of industry standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate2 Synchro-

nous DRAMs (DDR2 SDRAMs) with 1.8V +/-

0.1V Power Supply

All inputs and outputs are compatible with

SSTL_1.8 interface

8 Bank architecture

Posted CAS

Programmable CAS Latency 3, 4, 5, 6

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

•

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60 ball(x4/x8)

133.35 x 30.00 mm form factor

Halogen free & RoHS compliant

•

ORDERING INFORMATION

Part Name

HMP112P7EFR8C-C4/Y5/S6/S5

HMP125P7EFR4C-C4/Y5/S6/S5

HMP151P7EFR4C-C4/Y5/S6/S5

HMP31GP7EMR4C-C4/Y5

Density Organization

1GB

2GB

4GB

8GB

128Mx72

256Mx72

512Mx72

# of

DRAMs

# of

ranks

Materials

Halogen Free

Parity

Support

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Sep. 2008

HMP112P7EFR4C-S5 Related Products

	HMP112P7EFR4C-S5	HMP112P7EFR4C-Y5	HMP112P7EFR4C-C4	HMP112P7EFR4C-S6
Description	DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 128MX8, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 128MX8, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
Is it Rohs certified?	conform to	conform to	conform to	conform to
Parts packaging code	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM,	DIMM,	HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
Contacts	240	240	240	240
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
JESD-30 code	R-PBGA-B60	R-PBGA-B84	R-XZMA-N200	R-PBGA-B60
length	133.35 mm	133.35 mm	133.35 mm	133.35 mm
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	8	8	8	8
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	240	240	240	240
word count	134217728 words	134217728 words	134217728 words	134217728 words
character code	128000000	128000000	128000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	55 °C	55 °C	55 °C	55 °C
organize	128MX8	128MX8	128MX8	128MX8
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	MICROELECTRONIC ASSEMBLY	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	30 mm	30 mm	30 mm	30 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	ZIG-ZAG	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	2.7 mm	2.7 mm	2.7 mm	2.7 mm
Base Number Matches	1	1	1	-
Maker	-	SK Hynix	SK Hynix	SK Hynix

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