Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
FEDL63512A-03
¡ Semiconductor
ML63512A/63514A
GENERAL DESCRIPTION
This version: Feb. 2000
Previous version: Jul. 1999
4-Bit Microcontroller with Built-in Level Detector, Melody Circuit, and Comparator,
Operating at 0.9 V (Min.)
The ML63512A/63514A is a CMOS 4-bit microcontroller with built-in level detector and
operates at 0.9 V (min.).
The ML63512A/63514A is an M63512 series mask ROM-version product of OLMS-63K family,
which employs Oki's original CPU core nX-4/250.
The program memory capacity and data memory capacity of the ML63512A differ from those of
the ML63514A.
48-pin TQFP and 64-pin TQFP packages are available for the ML63512A and ML63514A.
FEATURES
• Extensive instruction set
407 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, stack operations, flag operations,
jump, conditional branch, call/return, control.
• Wide variety of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61
ms
(@ 32.768 kHz system clock)
1
ms
(@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: Crystal oscillation or RC oscillation selectable by
mask option (30 to 80 kHz)
: Ceramic oscillation or RC oscillation selectable by
mask option (2 MHz max.)
• Program memory space
ML63512A: 4K words
ML63514A: 8K words
Basic instruction length is 16 bits/1 word
• Data memory space
ML63512A: 128 nibbles
ML63514A: 256 nibbles
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FEDL63512A-03
¡ Semiconductor
• Stack level
Call stack level
Register stack level
ML63512A/63514A
: 16 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistor/high-impedance input
Output ports: N-channel open drain output (can directly drive LEDs)
Input-output ports: Selectable as input with pull-up resistor/high-impedance input
Selectable as N-channel open drain output/CMOS output
Can be interfaced with external peripherals that use a different power supply than this device
uses. (Power to the output port is supplied from V
DDI
(separate power suply))
Number of ports:
(For 48-pin packages)
Input port
: 1 port
¥
4 bits
Output port
: 1 port
¥
4 bits
Input-output port
: 6 ports
¥
4 bits
(For 64-pin packages and chips)
Input port
: 1 port
¥
4 bits
Output port
: 1 port
¥
4 bits
Input-output port
: 9 ports
¥
4 bits
• Melody output function
Melody sound frequency
Tone length
Tempo
Melody data
Number of output ports
Buzzer driver signal output
• Level detector
Conversion time
Dedicated input pins
Detection level
• Comparator
Offset voltage
Comparison time
Number of channels
:
:
:
:
:
:
529 to 2979 Hz (@ 32.768 kHz)
63 varieties
15 varieties
Stored in the program memory
1 (dedicated pin)
4 kHz (@ 32.768 kHz)
: Approx. 183
ms
(@ 32.768 kHz)
: 2 pins (switched by software; for the secondary
functions of the input ports)
: 12 levels
: 50 mV max. (V
DD
= 1.5 V)
: Approx. 183
ms
(@ 32.768 kHz)
: 1 (for the secondary functions of the input ports)
• System reset function
System reset through RESETB pin (connected to the internal 32 kHz sampling circuit)
(RESETB pin can be pulled up by mask option)
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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FEDL63512A-03
¡ Semiconductor
ML63512A/63514A
• Timers and counter
8-bit timer
¥
2
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
15-bit time base counter
¥
1
1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 128 Hz, 256 Hz, 512 Hz, 1 kHz, and 2 kHz signals
can be read (@ 32.768 kHz)
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
• Interrupt sources
External interrupt (4 sources)
Internal interrupt (10 sources)
: Selectable as UART mode/synchronous
mode
: 2TBCCLK, TBCCLK, 1/2TBCCLK, Timers 0
& 1 overflow
24 kbps Max. (when 2TBCCLK @ 80 kHz
selected)
: 30 to 80 kHz (internal clock mode), external
clock frequency
: 5 to 8 bits
: Selectable as rising edge/falling edge/both
rising and falling edges
: Time base interrupt
¥
4 (2, 4, 16, and 32 Hz
@ 32.768 kHz)
Timer interrupt
¥
2
Level detector interrupt
¥
1
Serial port reception interrupt
¥
1
Serial port transmission interrupt
¥
1
Melody end interrupt
¥
1
• Operating temperature
–20 to +70°C
• Supply voltage
When backup used
When backup not used
: 0.9 to 1.8 V
(Maximum operating frequency 1 MHz)
: 1.8 to 3.5 V
(Maximum operating frequency 2 MHz;
when Level detector or Comparator is
used)
1.8 to 5.5 V
(Maximum operating frequency 2 MHz;
when Level detector and Comparator are
not used)
• Package options:
Chip (60 pads)
: (Product name: ML63512A-xxxWA,
ML63514A-xxxWA)
48-pin plastic TQFP (TQFP48-P-0707-0.50-K) : (Product name: ML63512A-xxxTB,
ML63514A-xxxTB)
64-pin plastic TQFP (TQFP64-P-1010-0.50-K) : (Product name: ML63512A-xxxTP,
ML63514A-xxxTP)
xxx indicates a code number.
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FEDL63512A-03
¡ Semiconductor
ML63512A/63514A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. The power to the circuits corresponding
to the signal names inside
is supplied from V
DDI
(power supply for interface).
CPU CORE
CBR
H
nX-4/250
L
RA
PC
ROM
ML63512A: 4KW
ML63514A: 8KW
TIMING
CON-
TROL
EBR
SP
RSP
X
Y
C
A
G
MIE
Z
BUS
CON-
TROL
ALU
STACK
CAL: 16-level
REG: 16-level
INSTRUCTION
DECODER
IR
INT
2
RESETB
RST
RAM
ML63512A: 128N
ML63514A: 256N
INT
TST1B
TST2B
TST
INT
2
SIO
INT
1
OSC
MELODY
INT
4
TBC
DATA BUS
TIMER
8bit
¥
2
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T0CK*
T1CK*
RXD*
TXC*
RXC*
TXD*
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
MD
P0.0-P0.3
P1.0-P1.3
P2.0-P2.3
P3.0-P3.3
I/O
PORT
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
=
INT
1
LDIN0*
LDIN1*
Level
Detector
CMPIN*
CMPREF*
CMP
V
DDH
V
DD
CB1
CB2
BACK-
UP
INT
4
P9.0-P9.3
=
PA.0-PA.3
=
V
DDL
VR
INPUT
PORT
P7.0-P7.3
OUTPUT
PORT
P8.0-P8.3
V
DDI
V
SS
=
Port 6 (P6.0 to P6.3), Port 9 (P9.0 to P9.3) and Port A (PA.0 to PA.3) are provided for the 64-pin
packages and chips.
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