EEWORLDEEWORLDEEWORLD

Part Number

Search

SI4123G-BMR

Description
RF and Baseband Circuit, MLP-28
CategoryAnalog mixed-signal IC    The signal circuit   
File Size702KB,32 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

SI4123G-BMR Overview

RF and Baseband Circuit, MLP-28

SI4123G-BMR Parametric

Parameter NameAttribute value
Parts packaging codeDFN
package instructionHVQCCN,
Contacts28
Reach Compliance Codeunknown
Is SamacsysN
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeS-XQCC-N28
length5 mm
Number of functions1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-20 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification statusNot Qualified
Maximum seat height0.9 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
Temperature levelOTHER
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
width5 mm
Base Number Matches1
Si4133G
Si4123G/22G/13G/12G
D
UAL
-B
AND
RF S
YNTHESIZER
W
ITH
I
NTEGRATED
VCO
S
F
OR
GSM
AND
GPRS W
IRELESS
C
OMMUNICATIONS
Features
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
33
S
i4
1
G
-B
T
Dual-band RF Synthesizers
IF synthesizer: 500 to
1000 MHz
Integrated VCOs, loop filters,
varactors, and resonators
Minimal number of external
components required
Fast settling time: 140
µs
GPRS Class 12 compliant
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP and
28-pin MLP
Ordering Information:
See page 28.
Applications
GSM 850, E-GSM 900, DCS 1800, and PCS 1900 cellular
telephones
GPRS data terminals
HSCSD data terminals
Pin Assignments
Si4133G-BT
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
Description
The Si4133G is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. The Si4133G includes three VCOs, loop filters, reference
and VCO dividers, and phase detectors. Divider and powerdown settings
are programmable with a three-wire serial interface.
Functional Block Diagram
Reference
Amplifier
Power
Down
Control
GNDR
RFOUT
VDDR
XIN
÷
65
Phase
Detector
RF1
RFLA
RFLB
PWDN
SDATA
IFOUT
23
GNDR
SCLK
SDATA
SCLK
SEN
Serial
Interface
22-bit
Data
Register
Phase
Detector
RF2
RFLC
RFLD
GNDR
RFLD
RFLC
1
2
3
4
5
6
7
28
27
26
25
24
22
21
20
19
GNDI
SEN
VDDI
÷
N
Si4133G-BM
RFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
÷
N
Phase
Detector
IF
IFOUT
IFLA
IFLB
AUXOUT
Test
Mux
GNDR
RFLB
RFLA
GNDR
GND
Pad
18
17
16
15
÷
N
8
9
10
11
12
13
14
RFOUT
AUXOUT
GNDR
GNDR
Patents pending
Rev. 1.4 5/03
Copyright © 2003 by Silicon Laboratories
Si4133G-DS14
PWDN
GNDD
VDDR

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号