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256-Position, Ultralow Power
1.8 V Logic-Level Digital Potentiometer
AD5165
FEATURES
Ultralow standby power I
DD
= 50 nA typical
256-position
End-to-end resistance 100 kΩ
Logic high voltage 1.8 V
Power supply 2.7 V to 5.5 V
Low temperature coefficient 35 ppm/°C
Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package
Simple 3-wire digital interface
Wide operating temperature −40°C to +125°C
Pin-to-pin compatible to AD5160 with CS inverted
FUNCTIONAL BLOCK DIAGRAM
V
DD
A
CS
SDI
CLK
3-WIRE
INTERFACE
W
WIPER
REGISTER
B
04749-0-001
GND
APPLICATIONS
Battery-operated electronics adjustment
Remote utilities meter adjustment
Mechanical potentiometer replacement
Transducer circuit adjustment
Automotive electronics adjustment
Gain control and offset adjustment
System calibration
VCXO adjustment
Figure 1.
PIN CONFIGURATION
W
1
8
A
04749-0-002
AD5165
7
B
V
DD 2
TOP VIEW
GND
3
(Not to Scale)
6
CS
5
SDI
CLK
4
Figure 2.
GENERAL OVERVIEW
The AD5165 provides a compact 2.9 mm × 2.8 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance. The AD5165’s supply voltage requirement is 2.7 V
to 5.5 V, but its logic voltage requirement is 1.8 V to V
DD
. The
AD5165 consumes very low quiescent power during standby
mode and is ideal for battery-operated applications.
Wiper settings are controlled through a simple 3-wire interface.
The interface is similar to the SPI® digital interface except for the
inverted chip-select function that minimizes logic power con-
sumption in the idling state. The resistance between the wiper
and either endpoint of the fixed resistor varies linearly with
respect to the digital code transferred into the wiper register.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 50 nA typical standby power allows use in battery-
operated portable or remote utility device applications.
TYPICAL APPLICATION
5V
V
OH
= 1.8V MIN
V
DD
3.3V
AD5165
CS
CLK
SDI
GND
V
A
V
W
WIDE TERMINAL
VOLTAGE RANGE:
0V < V
A
,V
B
,V
W
< 5V
04749-0-003
DIGITAL
CONTROL
LOGIC OR
MICRO
V
B
Figure 3.
Note:
The terms
digital potentiometer, RDAC,
and
VR
are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5165
TABLE OF CONTENTS
Electrical Characteristics—100 kΩ Version .................................. 3
Absolute Maximum Ratings............................................................ 5
Pin Configuration and Functional Descriptions.......................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
3-Wire Digital Interface................................................................. 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor ......................................... 13
Programming the Potentiometer Divider ............................... 14
3-Wire Serial Bus Digital Interface .......................................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Evaluation Board ........................................................................ 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5165
ELECTRICAL CHARACTERISTICS—100 kΩ VERSION
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.
Table 1.
Parameter
Symbol
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
2
Resistor Integral Nonlinearity
R-INL
Nominal Resistor Tolerance
3
∆R
AB
/R
AB
Resistance Temperature Coefficient
(∆R
AB
/R
AB
)/∆Tx10
6
Wiper Resistance
R
W
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Resolution
N
4
Differential Nonlinearity
DNL
4
Integral Nonlinearity
INL
(∆V
W
/V
W
)/∆Tx10
6
Voltage Divider Temperature
Coefficient
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
RESISTOR TERMINALS
Voltage Range
5
V
A,B,W
6
Capacitance A, B
C
A,B
Capacitance
6
W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current
C
W
I
CM
V
IH
V
IL
C
IL
V
DD RANGE
I
DD
Conditions
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
V
DD
= 2.7 V/5.5 V
Min
−1
−2
−20
Typ
1
±0.1
±0.25
35
85/50
Max
+1
+2
+20
150/120
8
+1
+1
Unit
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
pF
V
µA
µA
µA
µW
%/%
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−0.5
0
GND
f = 1 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
V
A
= V
B
= V
DD
/2
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.7 V to 5.5 V
1.8
±0.1
±0.3
15
−0.3
0.1
0
0.5
V
DD
90
95
1
0.6
5
2.7
5.5
1
Power Dissipation
7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 8
Bandwidth −3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
P
DISS
PSS
Digital inputs = 0 V or V
DD
V
DD
= 2.7 V, digital inputs = 1.8 V
V
DD
= 5 V, digital inputs = 1.8 V
Digital inputs = 0 V or V
DD
V
DD
= +5 V ± 10%,
Code = Midscale
Code = 0x80
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz,
V
A
= 5 V, V
B
= 0 V,
±1 LSB error band
R
WB
= 50 kΩ
0.05
10
500
±0.001
5.5
±0.005
BW
THD
W
t
S
e
N_WB
55
0.05
2
28
kHz
%
µs
nV/√Hz
1
2
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
5
Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
Rev. 0 | Page 3 of 16
AD5165
TIMING CHARACTERISTICS—100 kΩ VERSION
V
DD
= +5 V ± 10%, or +3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
2, 3, 4
3-WIRE INTERFACE TIMING CHARACTERISTICS
(specifications apply to all parts)
Clock Frequency
f
CLK
= 1/( t
CH
+ t
CL
)
Input Clock Pulse Width
t
CH
, t
CL
Clock level high or low
Data Setup Time
t
DS
Data Hold Time
t
DH
CS Setup Time
t
CSS
CS Low Pulse Width
t
CSW
CLK Fall to CS Rise Hold Time
t
CSH0
CLK Fall to CS Fall Hold Time
t
CSH1
CS Fall to Clock Rise Setup
t
CS1
Min
Typ
1
Max
25
20
5
5
15
40
0
0
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
1
2
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
Guaranteed by design and not subject to production test.
3
All dynamic characteristics use V
DD
= 5 V.
4
See Figure 34 and Figure 35 for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
Rev. 0 | Page 4 of 16
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