M28F210
M28F220
2 Megabit (x8 or x16, Block Erase) FLASH MEMORY
PRELIMINARY DATA
DUAL x8 and x16 ORGANIZATION
SMALL SIZE PLASTIC PACKAGES TSOP48
and SO44
MEMORY ERASE in BLOCKS
– One 16K Byte or 8K Word Boot Block (top or
bottom location) with hardware write and
erase protection
– Two 8K Byte or 4K Word Key Parameter
Blocks
– One 96K Byte or 48K Word Main Block
– One 128K Byte or 64K Word Main Blocks
5V
±
10% SUPPLY VOLTAGE
12V
±
5% or
±
10% PROGRAMMING
VOLTAGE
100,000 PROGRAM/ERASE CYCLES
PROGRAM/ERASE CONTROLLER
AUTOMATIC STATIC MODE
LOW POWER CONSUMPTION
– 60µA Typical in Standby
– 0.2µA Typical in Deep Power Down
– 15/20mA Typical Operating Consumption
(Byte/Word)
HIGH SPEED ACCESS TIME: 70ns
EXTENDED TEMPERATURE RANGES
Table 1. Signal Names
A0-A16
DQ0-DQ7
DQ8-DQ14
DQ15A-1
E
G
W
BYTE
RP
V
PP
V
CC
V
SS
February 1996
Address Inputs
Data Input / Outputs
Data Input / Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Byte/Word Organization
Reset/Power Down/Boot Block
Unlock
Program & Erase Supply Voltage
Supply Voltage
Ground
44
1
TSOP48 (N)
12 x 20mm
SO44 (M)
Figure 1. Logic Diagram
VCC
VPP
17
A0-A16
15
RP
W
E
G
M28F210
M28F220
DQ0-DQ14
BYTE
DQ15A-1
VSS
AI01297
1/42
This is preliminary infor mationon a new product now in developmen t or undergoing evaluation. Details are subject to change without notice.
M28F210, M28F220
Figure 2A. TSOP Pin Connections
Figure 2B. SO Pin Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
VPP
DU
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
48
12
13
M28F210
M28F220
(Normal)
37
36
24
25
AI01798
A16
BYTE
VSS
DQ15A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
VPP
DU
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M28F210 34
12 M28F220 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI01299
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
Warning:
NC = Not Connected, DU = Don’t Use
Warning:
DU = Don’t Use
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2, 3)
V
CC
V
A9 (2)
V
PP
(2)
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9 Voltage
Program Supply Voltage, during Erase
or Programming
RP Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
–0.6 to 14
–0.6 to 13.5
Unit
°C
°C
°C
V
V
V
V
V
V
RP (2)
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Maximum DC voltage on I/O is V
CC
+ 0.5V, overshoot to 7V allowed for less than 20ns.
2/42
M28F210, M28F220
Table 3. Operations
Operation
Read Word
Read Byte
Write Word
Write Byte
Output Disable
Standby
Power Down
E
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
X
G
V
IL
V
IL
V
IH
V
IH
V
IH
X
X
W
V
IH
V
IH
V
IL
V
IL
V
IH
X
X
RP
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
BYTE
V
IH
V
IL
V
IH
V
IL
X
X
X
DQ0 - DQ7
Data Output
Data Output
Data Input
Data Input
Hi-Z
Hi-Z
Hi-Z
DQ8 - DQ14
Data Output
Hi-Z
Data Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ15A-1
Data Output
Address Input
Data Input
Address Input
Hi-Z
Hi-Z
Hi-Z
Note:
X = V
IL
or V
IH
, V
PP
= V
PPL
or V
PPH
Table 4. Electronic Signature
Organis
ation
Code
Manufact.
Code
Word-
wide
Device
Code
M28F210
M28F220
Manufact.
Code
Byte-
wide
Device
Code
M28F210
M28F220
Note:
RP = V
IH
Device
E
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
G
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
W
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
BYTE
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
A0
V
IL
V
IH
V
IH
V
IL
V
IH
V
IH
A9
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
A1-A8 &
A10-A16
Don’t
Care
Don’t
Care
Don’t
Care
Don’t
Care
Don’t
Care
Don’t
Care
DQ0 -
DQ7
20h
0E0h
0E6h
20h
0E0h
0E6h
DQ8 -
DQ14
00h
00h
00h
Hi-Z
Hi-Z
Hi-Z
DQ15
A-1
0
0
0
Don’t
Care
Don’t
Care
Don’t
Care
DESCRIPTION
The M28F210 and M28F220 FLASH MEMORIES
are non-volatile memories that may be erased
electrically at the block level and programmed by
byte or word. The interface is directly compatible
with most microprocessors. SO44 and TSOP48
packages are used.
Organization
The organization, as 256K x 8 or 128K x 16, is
selectable by an external BYTE signal. When
BYTE is Low the x8 organization is selected, the
Data Input/Output signal DQ15 acts as Address
line A-1 and selects the lower or upper byte of the
memory word for output on DQ0-DQ7, DQ8-DQ14
remain high impedance. When BYTE is High the
memory uses the Address inputs A0-A16 and the
Data Input/OutputsDQ0-DQ15. Memory control is
provided by Chip Enable, Output Enable and Write
Enable inputs. A Reset/Power Down/Boot block
unlock, tri-level input, places the memory in deep
power down, normal operation or enables pro-
gramming and erasure of the Boot block.
3/42
M28F210, M28F220
Table 5. Instructions
Mnemo
nic
Instruction
Read
Memory
Array
Read
Status
Register
Read
Electronic
Signature
Erase
Program
Clear
Status
Register
Erase
Suspend
Erase
Resume
Cycles
Operation
1+
Write
1st Cycle
Address
X
(1)
2nd Cycle
Data
(4)
Operation
Read
(2)
Address
Read
Address
Data
Data
RD
0FFh
RSR
1+
Write
X
70h
Read
(2)
X
Status
Register
RSIG
3
Write
X
90h
Read
(2)
Signature
(3)
Adress
Block
Address
Address
Signature
EE
PG
CLRS
2
2
1
Write
Write
Write
X
X
X
20h
40h or 10h
50h
Write
Write
0D0h
Data Input
ES
ER
1
1
Write
Write
X
X
0B0h
0D0h
Notes:
1. X = Don’t Care.
2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations to read memory array, Status Register
or Electronic Signature codes. Any number of Read cycle can occur after one command cycle.
3. Signature address bit A0=V
IL
will output Manufacturer code. Address bit A0=V
IH
will output Device code. Other address bits are
ignored.
4. When word organization is used, upper byte is don’t care for command input.
Table 6. Commands
Hex Code
00h
10h
20h
40h
50h
70h
90h
0B0h
0D0h
0FFh
Command
Invalid/Reserved
Alternative Program Set-up
Erase Set-up
Program Set-up
Clear Status Register
Read Status Register
Read Electronic Signature
Erase Suspend
Erase Resume/Erase Confirm
Read Array
Blocks
Erasure of the memories is in blocks. There are 5
blocks in the memory address space, one Boot
Block of 16K Bytes or 8K Words, two ’Key Parame-
ter Blocks’ of 8K Bytes or 4K Words, one ’Main
4/42
Block’ of 96K Bytes or 48K Words, and one ’Main
Block’ of 128K Bytes or 64K Words. The M28F210
memory has the Boot Block at the top of the mem-
ory address space (1FFFFh) and the M28F220
locates the Boot Block starting at the bottom
(00000h). Erasure of each block takes typically 1
second and each block can be programmed and
erased over 100,000 cycles.
The Boot Block is hardware protected from acci-
dental programming or erasure depending on the
RP signal. Program/Erase commands in the Boot
Block are executed only when RP is at 12V. Block
erasure may be suspended while data is read from
other blocks of the memory, then resumed.
Bus Operations
Six operationscan beperformed by the appropriate
bus cycles, Read Byte or Word from the Array,
Read Electronic Signature, Output Disable,
Standby, Power Down and Write the Command of
an Instruction.
Command Interface
Commands can be written to a Command Interface
(C.I.) latch to perform read, programming, erasure
and to monitor the memory’s status. When power
M28F210, M28F220
Table 7. Status Register
Mnemon
ic
Bit
Name
Logic
Level
’1’
P/ECS
7
P/E.C. Status
’0’
Erase
Suspend
Status
’1’
’0’
’1’
ES
5
Erase Status
’0’
’1’
’0’
’1’
VPPS
3
V
PP
Status
’0’
2
1
0
Reserved
Reserved
Reserved
V
PP
OK
Erase Success
Program Error
Program
Success
V
PP
Low, Abort
Busy
Suspended
In progress or
Completed
Erase Error
Definition
Ready
Note
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
ESS
6
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
PS
4
Program
Status
PS bit set to ’1’ if the P/E.C. has failed to program
a byte or word.
VPPS bit is set if the V
PP
voltage is below
V
PPH
(min) when a Program or Erase instruction
has been executed.
Notes:
Logic level ’1’ is High, ’0’ is Low.
is first applied, on exit from power down or if V
CC
falls below V
LKO
, the command interface is reset to
Read Memory Array.
Instructions and Commands
Eight Instructions are defined to perform Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, Erase, Program, Clear Status
Register, Erase Suspend and Erase Resume. An
internalProgram/EraseController (P/E.C.) handles
all timing and verification of the Program and Erase
instructions and provides status bits to indicate its
operation and exit status. Instructions are com-
posed of a first command write operation followed
by either second command write, to confirm the
commands for programming or erase, or a read
operationto read data from the array, the Electronic
Signature or the Status Register.
For added data protection, the instructions for byte
or word program and block erase consist of two
commands that are written to the memory and
which start the automatic P/E.C. operation. Byte or
word programming takes typically 9µs, block erase
typically 1 second. Erasure of a memory block may
be suspended in order to read data from another
block and then resumed. A Status Register may be
read at any time, including during the programming
or erase cycles, to monitor the progress of the
operation.
Power Saving
The M28F210 and M28F220 have a number of
power saving features. A CMOS standby mode is
entered when the Chip Enable E and the Re-
set/Power Down (RP) signals are at V
CC
, when the
supply current drops to typically 60µA. A deep
power down mode is enabled when the Re-
set/Power Down (RP) signal is at V
SS
, when the
supply current drops to typically 0.2µA. The time
required to awake from the deep power down mode
is 300ns maximum, with instructions to the C.I.
recognised after only 210ns.
5/42
ADI Reference Circuit
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