MMPQ3467
INFORMATION FOR USING THE SO−16 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the to-
tal design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the cor-
rect pad geometry, the packages will self align when sub-
jected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
inches
mm
0.024
0.6
0.050
1.270
SO−16
SO−16 POWER DISSIPATION
The power dissipation of the SO−16 is a function of the
pad size. This can vary from the minimum pad size for sol-
dering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T
J(max)
, the maximum rated junction temperature of the
die, R
θJA
, the thermal resistance from the device junction
to ambient, and the operating temperature, T
A
. Using the
values provided on the data sheet for the SO−16 package,
P
D
can be calculated as follows:
P
D
=
T
J(max)
−
T
A
R
θJA
SOLDERING PRECAUTIONS
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T
A
of 25°C,
one can calculate the power dissipation of the device which
in this case is 1.0 watt.
P
D
=
150°C
−
25°C
125°C/W
= 1.0 watt
The 125°C/W for the SO−16 package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.0 watt. There are
other alternatives to achieving higher power dissipation
from the SO−16 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad™. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can
be doubled using the same footprint.
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in or-
der to minimize the thermal stress to which the devices are
subjected.
•
Always preheat the device.
•
The delta temperature between the preheat and solder-
ing should be 100°C or less.*
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum tem-
perature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering meth-
od, the difference shall be a maximum of 10°C.
•
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•
When shifting from preheating to soldering, the maxi-
mum temperature gradient shall be 5°C or less.
•
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•
Mechanical stress or shock should not be applied dur-
ing cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
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MMPQ3467
PACKAGE DIMENSIONS
CASE 751B−05
SO−16
ISSUE J
−A−
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.229
0.244
0.010
0.019
−B−
1
8
P
8 PL
0.25 (0.010)
M
B
S
G
K
C
−T−
SEATING
PLANE
R
X 45
_
F
D
16 PL
M
0.25 (0.010)
T B
S
A
S
M
J
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MMPQ3467/D
FPGA/CPLD
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