MX29F400CBMI-55G datasheet, PDF

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MX29F400CBMI-55G: DescriptionFlash, 256KX16, 55ns, PDSO44, 0.500 INCH, ROHS COMPLIANT, MO-175, SOP-44; Categorystorage storage; File Size741KB，47 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx; Environmental Compliance

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MX29F400CBMI-55G Overview

Flash, 256KX16, 55ns, PDSO44, 0.500 INCH, ROHS COMPLIANT, MO-175, SOP-44

MX29F400CBMI-55G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1125521126
package instruction	SOP, SOP44,.63
Reach Compliance Code	unknown
ECCN code	EAR99
YTEOL	0
Maximum access time	55 ns
Other features	BOTTOM BOOT
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Data polling	YES
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G44
JESD-609 code	e3
length	28.5 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of departments/size	1,2,1,7
Number of terminals	44
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP44,.63
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Programming voltage	5 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	3 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	12.6 mm

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MX29F400C T/B

4M-BIT [512K x 8 / 256K x 16] SINGLE VOLTAGE

5V ONLY FLASH MEMORY

FEATURES

GENERAL FEATURES

• Single Power Supply Operation

- 4.5 to 5.5 volt for read, erase, and program operations

• 524,288 x 8 / 262,144 x 16 switchable

• Boot Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Sector Structure

- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 7

• Sector protection

- Hardware method to disable any combination of sectors from program or erase operations

- Temporary sector unprotected allows code changes in previously locked sectors

• Latch-up protected to 100mA from -1V to Vcc + 1V

• Compatible with JEDEC standard

- Pinout and software compatible to single power supply Flash

PERFORMANCE

• High Performance

- Access time: 70/90ns

- Byte/Word program time: 9us/11us (typical)

- Erase time: 0.7s/sector, 4s/chip (typical)

• Low Power Consumption

- Low active read current: 40mA (maximum) at 5MHz

- Low standby current: 1uA (typical)

• Minimum 100,000 erase/program cycle

• 20 years data retention

SOFTWARE FEATURES

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data from or program data to another sector which is not being

erased

• Status Reply

- Data# Polling & Toggle bits provide detection of program and erase operation completion

HARDWARE FEATURES

• Ready/Busy# (RY/BY#) Output

- Provides a hardware method of detecting program and erase operation completion

• Hardware Reset (RESET#) Input

- Provides a hardware method to reset the internal state machine to read mode

PACKAGE

• 44-Pin SOP

• 48-Pin TSOP

•

All devices are RoHS Compliant

•

All non RoHS Compliant devices are not recommeded for new design in

P/N:PM1200

Rev. 2.3, December 14, 2017

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