P4C1048L
LOW POWER 512K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—45/55/70/100 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP II
DESCRIPTION
The P4C1048L is a 4 Megabit low power CMOS static
RAM organized as 512K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 45 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1048L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
18
. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either
CE
is HIGH or
WE
is LOW.
The P4C1048L is packaged in a 32-pin 445 mil plastic
SOP, 32-pin TSOP II, or 600 mil plastic or ceramic side-
brazed DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10),
SOP (S12), TSOP II (T4)
TOP VIEW
Document #
SRAM129
REV D
Revised July 2007
1
P4C1048L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Military (-55°C to 125°C)
Supply Voltage
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
MAXIMUM RATINGS
(a)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
CAPACITANCES
(d)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
6
8
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
Temperature Range
Commercial
I
CC
Dynamic Operating Current Industrial
Military
*
-45
20
25
35
-55
20
25
35
-70
20
25
35
-100
20
25
35
mA
Unit
*Tested
with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e.
CE
and
WE
≤
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
Notes:
a. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability.
b. Extended temperature operation guaranteed with 400 linear feet per minute of air flow.
c. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
d. This parameter is sampled and not 100% tested.
Document #
SRAM129
REV D
Page 2 of 12
P4C1048L
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
(b)
Symbol
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
I
OL
= +2.1 mA, V
CC
= Min.
I
OH
= –1 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
I
LO
Output Leakage Current
CE
= V
IH
,
V
OUT
= GND to V
CC
I
SB
Standby Power Supply
Current (TTL Input Levels) V
CC
= Max,
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
V
CC
= Max,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
N/A = Not Applicable
Test Conditions
P4C1048L
Unit
Min
Max
V
CC
+0.5 V
2.2
0.8
–0.5
(c)
V
CC
–0.2 V
CC
+0.5
–0.5
(c)
0.2
0.4
2.4
Mil.
Ind./Com’l.
Mil.
Ind./Com’l.
–10
–5
–10
–5
+10
+5
+10
+5
µA
V
V
V
V
V
µA
I
LI
CE
≥
V
IH
Mil.
Ind./Com’l.
___
___
5
3
mA
Mil.
Ind./Com’l.
___
___
100
30
µA
I
SB1
Document #
SRAM129
REV D
Page 3 of 12
P4C1048L
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low to
Low Z
Output Enable High
to High Z
Chip Enable to Power
Up Time
Chip Disable to
Power Down Time
0
45
5
18
0
55
5
10
18
22
5
20
0
70
-45
Min Max
45
45
45
5
10
20
25
5
25
0
100
-55
Min Max
55
55
55
5
10
25
35
5
35
-70
Min Max
70
70
70
5
10
35
45
-100
Min
Max
100
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
Document #
SRAM129
REV D
Page 4 of 12
P4C1048L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
CE
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
and
OE
are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
transition LOW.
4. Transition is measured ± 200 mV from steady state voltage prior to change,
with loading as specified in Figure 1. This parameter is sampled and not
100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM129
REV D
Page 5 of 12
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