Data Sheet
March 2011
AR8035 Integrated 10/100/1000 Gigabit
Ethernet Transceiver
General Description
The AR8035 is part of the Arctic family of
devices - which includes the AR8031, AR8033,
and the AR8035. It is Atheros’ 4
th
generation,
single port 10/100/1000 Mbps Tri-speed
Ethernet PHY. It supports RGMII interface to
the MAC.™
The AR8035 provides a low power, low BOM
(Bill of Materials) cost solution for
comprehensive applications including
consumer, enterprise, carrier and home
networks such as PC, HDTV, Gaming
machines, Blue-ray players, IPTV STB, Mdia
Players, IP Cameras, NAS, Printers, Digital
Photo Frames, MoCA/Homeplug
(Powerline)/EoC/ adapters and Home Router
& Gateways, etc.
The AR8035 integrates Atheros latest Green
Ethos
®
power saving technologies and
significantly saves power not only during work
time, but also during overtime. Atheros Green
Ethos
®
power savings include ultra-low power
in cable unplugged mode or port power down
mode, and automatic optimized power saving
based on cable length. Furthermore, the
AR8035 supports Wake-on-LAN (WoL) feature
to be able to help manage and regulate total
system power requirements.
The AR8035 embeds CDT (Cable Diagnostics
Test) technology on-chip which allows
customers to measure cable length, detect the
cable status, and identify remote and local PHY
malfunctions, bad or marginal patch cord
segments or connectors. Some of the possible
problems that can be detected include opens,
shorts, cable impedance mismatch, bad
connectors, termination mismatch, and a bad
transformer.
The AR8035 also integrates a voltage regulator
on chip. It reduces the termination R/C
circuitry on both the MAC interface (RGMII)
and line side.
The AR8035 supports IEEE 802.3az Energy
Efficient Ethernet (EEE) standard and Atheros
proprietary SmartEEE, which allows legacy
MAC/SoC devices without 802.3az support to
function as the complete 802.3az system. The
key features supported by the device are:
n
10BASE-Te PHY supports reduced transmit
amplitude.
n
100BASE-Tx and 1000BASE-T use Low
Power Idle (LPI) mode to turn off unused
analog and digital blocks to save power
while data traffic is in idle.
Features
n
10BASE-Te/100BASE-Tx/1000 BASE-T
n
n
n
n
IEEE 802.3 compliant
Supports 1000 BASE-T PCS and auto-
negotiation with next page support
Supports RGMII interface to MAC devices
with a broad I/O voltage level options
including 2.5V, 1.8V and 1.5V, and is
compatible with 3.3V I/O
RGMII timing modes support internal delay
and external delay on Rx path
Error-free operation up to 140 meters of
CAT5 cable
power saving modes with internal
automatic DSP power saving scheme
Supports 802.3az (Energy Efficient Ethernet)
Fully integrated digital adaptive equalizers,
echo cancellers, and near end crosstalk
(NEXT) cancellers
Supports Wake-on-LAN (WoL) to detect
magic packet and notify the sleeping system
to wake up
A robust Cable Discharge Event (CDE)
tolerence of ± 6kV
A robust surge protection with ±750V/
differential mode and ±4KV/common
mode
Jumbo Frame support up to 10KB (full
duplex)
All digital baseline wander correction
Automatic channel swap (ACS)
Automatic MDI/MDIX crossover
Automatic polarity correction
IEEE 802.3u compliant Auto-Negotiation
Software programmable LED modes
Multiple Loopback modes for diagnostics
n
Supports Atheros latest Green Ethos
®
n
n
n
n
n
n
n
n
n
n
n
n
n
© 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,
Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The
Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•
1
n
Cable Diagnostic Test (CDT)
n
Single power supply: 3.3V
n
5mm x 5mm. 40-pin QFN package
AR8035 Functional Block Diagram
DAC
Waveshape
Filter
Echo
Canceller
TRD[0:3]
Decision
Feedback
Equalizer
Symbol
Encoder
RGMII
PMA
Hybrid
Circut
PCS
Symbol
Decoder
RGMII
Next
Canceller
PGA
ADC
Feed
Forward
Equalizer
Deskewer
Trellis
Decoder
AGC
Timing and
Phase
Recovery
Auto-
Negotiation
MII Management
Registers
DLL
2
2
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AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver
March 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR8035 Functional Block Diagram .............. 2
3.4 MDIO Characteristics ............................ 22
3.5 XTAL/OSC characteristic table ........... 23
3.6 Power Pin Consumption ...................... 24
3.7 Typical Power Consumption Parameters
25
3.8 Power-on Sequence, Reset and Clock . 26
3.8.1 Power-on Sequence .................... 26
3.8.2 Reset and Clock Timing ............. 26
1 Pin Descriptions ............................ 3
2 Functional Description ................. 9
2.1 Transmit Functions ................................ 10
2.2 Receive Functions .................................. 10
2.2.1 Decoder Modes ........................... 10
2.2.2 Analog to Digital Converter ...... 10
2.2.3 Echo Canceller ............................. 10
2.2.4 NEXT Canceller .......................... 10
2.2.5 Baseline Wander Canceller ....... 10
2.2.6 Digital Adaptive Equalizer ....... 10
2.2.7 Auto-Negotiation ........................ 11
2.2.8 Smartspeed Function ................. 11
2.2.9 Automatic MDI/MDIX Crossover
11
2.2.10 Polarity Correction ..................... 11
2.3 Loopback Modes .................................... 11
2.3.1 Digital Loopback ......................... 11
2.3.2 External Cable Loopback ........... 11
2.3.3 Remote PHY Loopback .............. 12
2.4 Cable Diagnostic Test ............................ 12
2.5 LED Interface .......................................... 12
2.6 Power Supplies ....................................... 14
2.7 Management Interface .......................... 15
2.8 Atheros Green Ethos® .......................... 16
2.8.1 Low Power Modes ...................... 16
2.8.2 Shorter Cable Power Mode ....... 16
2.8.3 Hibernation Mode ...................... 16
2.9 IEEE 802.3az and Energy Efficient
Ethernet 17
2.9.1 IEEE 802.3az LPI Mode .............. 17
2.10 Atheros SmartEEE ................................ 18
2.11 Wake On LAN (WoL) ........................... 18
4 Register Descriptions ..................27
4.1 Register Summary ................................. 27
4.1.1 Control ......................................... 28
4.1.2 Status ............................................ 30
4.1.3 PHY Identifier [18:3] .................. 31
4.1.4 PHY Identifier [19:24] ................ 31
4.1.5 Auto-Negotiation Advertisement
31
4.1.6 Link Partner Ability (Base Page) 33
4.1.7 Auto-Negotiation Expansion .... 34
4.1.8 Next Page Transmit .................... 34
4.1.9 Link Partner Next Page ............. 35
4.1.10 1000 BASE-T Control ................. 35
4.1.11 1000 BASE-T Status .................... 37
4.1.12 MMD Access Address Register 38
4.1.13 MMD Access Control Register . 38
4.1.14 Extended Status .......................... 39
4.1.15 Function Control ......................... 39
4.1.16 PHY-Specific Status .................... 40
4.1.17 Interrupt Enable .......................... 41
4.1.18 Interrupt Status ........................... 42
4.1.19 Smart Speed ................................. 43
4.1.20 Cable Diagnostic Tester Control 43
4.1.21 LED Control ................................ 44
4.1.22 Cable Defect Tester Status ......... 45
4.1.23 Debug Port Address Offset ....... 45
4.1.24 Debug Port Data ......................... 45
4.2 Debug Register Descriptions ............... 46
4.2.25 rgmii rx clock delay control ...... 46
4.2.26 rgmii tx clock delay control ...... 46
4.2.27 Hib ctrl and rgmii gtx clock delay
register ......................................... 47
4.2.28 100BASE-TX Test Mode Select . 48
4.2.29 1000BT external loopback
3 Electrical Characteristics ............ 19
3.1 Absolute Maximum Ratings ................ 19
3.2 Recommended Operating Conditions 19
3.3 RGMII Characteristics ........................... 20
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver
March 2011
•
•
1
1
configure ...................................... 48
4.2.30 Rgmii_mode; Test configuration for
10BT .............................................. 49
4.2.31 MMD3 (MDIO Manageable Device
Address 3 for PCS) ..................... 49
4.2.32 MMD7 (MDIO Manageable Device
Address 7 for Auto-Negotiation) 50
5 MDIO Interface Register ........... 51
5.1 MMD3 - PCS Register ............................ 51
5.1.1 PCS Control 1 .............................. 51
5.1.2 PCS Status 1 ................................. 52
5.1.3 EEE Capability ............................ 53
5.1.4 EEE Wake Error Counter ........... 53
5.1.5 Wake-on-Lan loc_mac_addr_o . 54
5.1.6 Wake-on-Lan loc_mac_addr_o . 54
5.1.7 . Wake-on-Lan loc_mac_addr_o 54
5.1.8 Rem_phy_lpkb ............................ 55
5.1.9 Smart_eee control1 ..................... 55
5.1.10 Smart_eee control2 ..................... 55
5.1.11 Smart_eee control3 ..................... 56
5.1.1 AN status ..................................... 57
5.1.1 AN XNP transmit1 ..................... 57
5.1.1 AN XNP transmit2 ..................... 57
5.1.2 EEE advertisement ..................... 58
5.1.3 EEE LP advertisement ................ 58
6 Package Dimensions ..................... 1
7 Ordering Information ................... 1
8 Top-side Marking ......................... 1
2
2
•
•
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver
March 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
1. Pin Descriptions
This section contains a package pinout for the
AR8035 QFN 40 pin and a listing of the signal
descriptions (see
Figure 1-1).
The following nomenclature is used for signal
names:
NC
n
P
No connection to the internal die
is made from this pin
At the end of the signal name,
indicates active low signals
At the end of the signal name,
indicates the positive side of a
differential signal
At the end of the signal name
indicates he negative side of a
differential signal
The following nomenclature is used for signal
types described in
Table 1-1:
D
IA
I
IH
Open drain
Analog input signal
Digital input signal
Input signals with weak internal
pull-up, to prevent signals from
floating when left open
Input signals with weak internal
pull-down, to prevent signals
from floating when left open
A digital bidirectional signal
An analog output signal
A digital output signal
A power or ground signal
Internal pull-down for input
Internal pull-up for input
IL
N
I/O
OA
O
P
PD
PU
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver
March 2011
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