Preliminary Datasheet
LP1110
Dual Bootstrapped, 12V MOSFET Driver with Output Enable
General Description
The LP1110 is a single phase 12V MOSFET gate
driver optimized to drive the gates of both high-side
and low-side power MOSFETs in a synchronous buck
converter.
With a wide operating voltage range, high or low side
MOSFET gate drive voltage can be optimized for the
best efficiency. Internal adaptive non-overlap circuitry
further reduces switching
losses by preventing
simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST
voltages as high as 35V, with transient voltages as
high as 40V. Both gate outputs can be driven low by
applying a low logic level to the enable (EN) pin. An
under voltage lockout function ensures that both driver
outputs are low when the supply voltage is low, and a
Thermal Shutdown function provides the IC with
over-temperature protection.
C1
4
Features
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anti-cross Conduction Protection Circuitry
Applications
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Typical Application Circuit
VCC
D1
C2
VIN
M1
C3
LP1110
VCC
BST
DRVH
SWN
3
EN
DRVL
1
8
7
5
L1
VOUT
C4
EN
PWM
M2
Order Information
LP1110
□ □
□
F: Halogen Free & Pb Free
Package Type
QV:DFN-8
2
PWM
PGND
6
Marking Information
Device
LP1110
Marking
LPS
LP1110
YWX
Y:Production year
W:Production period X:Production batch
Package
DFN8
Shipping
5K/REEL
LP1110-01
May.-2018
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 1 of 8
Preliminary Datasheet
Functional Pin Description
Package Type
Pin Configurations
LP1110
BST
1
DFN8
8
7
6
5
DRVH
SWN
PGND
DRVL
PWM
2
EN
3
VCC
4
(TOP View)
Pin
Name
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and
1
BST
SW pins holds this bootstrap voltage for the high-side MOSFET as it is switched. The
recommended capacitor value is between 100nF and 1.0μF. An external diode is
required with the LP1110.
Logic-Level Input. This pin has primary control of the drive outputs.
Active high output enable. When low, normal operation is disabled forcing DRVH and
DRVL low.
Input Supply. A 1.0μF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
2
3
4
5
6
7
8
PWM
EN
VCC
DRVL
PGND
SWN
DRVH
LP1110-01
May.-2018
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 2 of 8
Preliminary Datasheet
Function Diagram
LP1110
BST
DRVH
SWN
LOGIC
Anti-Cross
Conduction
VCC
UVLO
PWM
EN
VCC
DRVL
OTP
PGND
Timing Diagram
EN
V
EN_LO
DRVH or DRVL
T
pdlEN
90%
10%
V
EN_HI
T
pdhEN
Figure 1.
V
PWM_HI
PWM
DRVL
T
pdlDRVL
T
fDRVL
90%
2V
10%
EN Timing waveforms
V
PWM_LO
90%
10%
T
pdhDRVH
T
rDRVH
DRVH-SWN
10%
90%
T
pdlDRVH
90%
T
fDRVH
T
rDRVL
2V
10%
T
pdhDRVL
SWN
Figure 2.
Input-Output Timing waveforms
LP1110-01
May.-2018
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 3 of 8
Preliminary Datasheet
Absolute Maximum Ratings
LP1110
VCC ----------------------------------------------------------------------------------------------------------------- -0.3V to 15V
BST ------------------------------------------------------------------------------------------------------------------ -0.3V to 35V
BST to SWN ------------------------------------------------------------------------------------------------------ -0.3V to 15V
SWN ------------------------------------------------------------------------------------------------------------------- -5V to 20V
DRVH ----------------------------------------------------------------------------------------------- SWN-0.3V to BST+0.3V
DRVL ------------------------------------------------------------------------------------------------------- -0.3V to VCC+0.3V
EN,PWM ---------------------------------------------------------------------------------------------------------- -0.3V to 6.5V
Maximum Junction Temperature ------------------------------------------------------------------------------------ 150℃
Maximum Soldering Temperature (at leads,10 sec) ----------------------------------------------------------- 260℃
Storage Temperature --------------------------------------------------------------------------------------- -65℃ to 150℃
Operating Ambient Temperature Range --------------------------------------------------------------- -40℃
to
85℃
Note1：All voltages are with respect to PGND except where noted.
Note2：Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note3: This device is ESD sensitive. Use standard ESD precautions when handling.
Thermal Information
Package Thermal Resistance (DFN-8,
Note4
)
Junction to Ambient,
θ
JA
---------------------------------------------------------------------------------------------- 70℃/W
Junction to Case,
θ
JC
--------------------------------------------------------------------------------------------------- 51℃/W
θ
JC
measured with reference to JEDEC 51-14.
Note4：
θ
JA
measured with reference to JEDEC51-2;
LP1110-01
May.-2018
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 4 of 8
Preliminary Datasheet
Electrical Characteristics
(VCC = 12 V, TA =25°C, unless otherwise noted.)
Characteristic
Supply
Supply Voltage Range
Supply Current
EN Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
PWM Input
Input Voltage High
Input Voltage Low
Hysteresis
Input Current
High-Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
trDRVH
tfDRVH
tpdhDRVH
Propagation Delay Times
tpdlDRVH
tpdlEN
tpdhEN
SW Pull-down Resistance
Low-Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
trDRVL
tfDRVL
tpdhDRVL
Propagation Delay Times
tpdlDRVL
tpdlEN
tpdhEN
Timeout Delay
Under Voltage Lockout
UVLO Startup
UVLO Shutdown
Hysteresis
−
−
−
−
−
−
-
-
-
−
VCC = PGND
CLOAD = 3.0 nF, (See Figure 2)
CLOAD = 3.0 nF, (See Figure 2)
(See Figure 1)
(See Figure 1)
DRVH
−
SWN = 0
−
−
−
−
−
-
-
-
−
−
BST
−
SWN = 12 V
BST
−
SWN = 12 V
BST
−
SWN = 0 V
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
BST
−
SWN = 12 V, CLOAD = 3.0 nF (See Figure 2)
(See Figure 1)
(See Figure 1)
SWN to PGND
−
−
−
−
−
-
VPWM_HI
VPWM_LO
−
−
−
−
−
No internal pull-up or pull-down resistors
2.0
−
−
−1.0
VEN_HI
VEN_LO
−
−
−
No internal pull-up or pull-down resistors
2.0
−
−
−1.0
VCC
ISYS
−
BST = 12 V, IN = 0 V, EN=0V
4.6
−
Symbol
Condition
Min
LP1110
Typ
−
0.7
−
−
300
−
−
−
300
−
3.3
0.5
15
30
12
95
15
30
35
15
3.3
0.5
15
30
12
105
15
30
35
110
4.3
4.0
0.3
Max
13.2
−
−
0.8
−
+1.0
−
0.8
−
+1.0
-
-
-
-
-
-
-
-
-
−
-
−
−
-
-
-
-
-
-
−
-
-
-
Unit
V
mA
V
V
mV
μA
V
V
mV
μA
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
kΩ
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
ns
V
V
V
LP1110-01
May.-2018
Email:
marketing@lowpowersemi.com
www.lowpowersemi.com
Page 5 of 8
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