a
FEATURES
8-/10-Channel, High Resolution - ADCs
AD7708 Has 16-Bit Resolution
AD7718 Has 24-Bit Resolution
Factory-Calibrated
Single Conversion Cycle Setting
Programmable Gain Front End
Simultaneous 50 Hz and 60 Hz Rejection
VREF Select™
Allows Absolute and Ratiometric
Measurement Capability
Operation Can Be Optimized for
Analog Performance (CHOP = 0) or
Channel Throughput (CHOP = 1)
INTERFACE
3-Wire Serial
SPI
TM
, QSPI
TM
, MICROWIRE
TM
, and DSP-Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.28 mA Typ @ 3 V
Power-Down: 30 A (32 kHz Crystal Running)
On-Chip Functions
Rail-to-Rail Input Buffer and PGA
2-Bit Digital I/O Port
APPLICATIONS
Industrial Process Control
Instrumentation
Pressure Transducers
Portable Instrumentation
Smart Transmitters
8-/10-Channel, Low Voltage,
Low Power, - ADCs
AD7708/AD7718
GENERAL DESCRIPTION
The AD7708/AD7718 are complete analog front-ends for low
frequency measurement applications. The AD7718 contains a
24-bit
Σ-∆
ADC with PGA and can be configured as 4/5 fully-
differential input channels or 8/10 pseudo-differential input
channels. Two pins on the device are configurable as analog
inputs or reference inputs. The AD7708 is a 16-bit version of
the AD7718. Input signal ranges from 20 mV to 2.56 V can be
directly converted using these ADCs. Signals can be converted
directly from a transducer without the need for signal conditioning.
The device operates from a 32 kHz crystal with an on-board PLL
generating the required internal operating frequency. The output
data rate from the part is software programmable. The peak-to-
peak resolution from the part varies with the programmed gain
and output data rate.
The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.84 mW typ.
Both parts are pin-for-pin compatible allowing an upgradable
path from 16 to 24 bits without the need for hardware modifica-
tions. The AD7708/AD7718 are housed in 28-lead SOIC and
TSSOP packages.
FUNCTIONAL BLOCK DIAGRAM
DVDD
DGND
REFIN2(+)/AIN9
REFIN1(+) REFIN2(–)/AIN10
REFIN1(–) XTAL1 XTAL2
OSC
AND
PLL
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
POS BUF
REFIN(+)
MUX
NEG BUF
PGA
REFIN(–)
- ADC*
*AD7708 16-BIT ADC
*AD7718 24-BIT ADC
AVDD
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT
DIN
SCLK
CS
RDY
RESET
AD7708/AD7718
AVDD
AGND
I/O PORT
P2
P1
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
VREF Select
is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD7708/AD7718
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 3
AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 6
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 9
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 10
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 15
Signal Chain Overview (CHOP Enabled, CHOP = 0) . . . 15
ADC NOISE PERFORMANCE CHOP ENABLED
(CHOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Signal Chain Overview (CHOP Disabled CHOP = 1) . . . 19
ADC NOISE PERFORMANCE CHOP DISABLED
(CHOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating Characteristics when Addressing the
Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 28
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ADC Offset Calibration Coefficient Registers . . . . . . . . . . . 31
ADC Gain Calibration Coefficient Register . . . . . . . . . . . . . 31
ID Register (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
User Nonprogrammable Test Registers . . . . . . . . . . . . . . . . 31
Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . . 32
DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AD7708/AD7718 to 68HC11 Interface . . . . . . . . . . . . . . . . 34
AD7708/AD7718-to-8051 Interface . . . . . . . . . . . . . . . . . . 35
AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . . . 36
BASIC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . 36
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Single-Ended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chop Mode of Operation (CHOP = 0) . . . . . . . . . . . . . . . . 37
Nonchop Mode of Operation (CHOP = 1) . . . . . . . . . . . . . 38
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . 38
Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . . . 38
Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
RESET
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programmable Logic Controllers . . . . . . . . . . . . . . . . . . . . . 41
Converting Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . . 42
Combined Ratiometric and Absolute Value
Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Optimizing Throughput while Maximizing 50 Hz
and 60 Hz Rejection in a Multiplexed Data
Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44
–2–
REV. 0
AD7708/AD7718
(AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V,
REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T
MIN
to
T
MAX
unless otherwise noted.)
Parameter
AD7718 (CHOP DISABLED)
Output Update Rate
No Missing Codes
2
Resolution
Output Noise and Update Rates
Integral Nonlinearity
Offset Error
3
Offset Error Drift vs. Temp
4
Full-Scale Error
3
Gain Drift vs. Temp
4
Negative Full-Scale Error
ANALOG INPUTS
Differential Input Full-Scale Voltage
B Grade
16.06
1.365
24
13
18
See Tables in
ADC Description
±
10
Table VII
±
200
±
10
±
0.5
±
0.003
Unit
Hz min
kHz max
Bits min
Bits p-p
Bits p-p
Test Conditions
CHOP = 1
±
20 mV Range, SF = 69
±
2.56 V Range, SF = 69
2 ppm Typical
Offset Error is in the order of the noise for the
programmed gain and update rate following a
calibration
AD7718 SPECIFICATIONS
1
ppm of FSR max
µV
typ
nV/°C typ
µV
typ
ppm/°C typ
% FSR max
±
1.024
×
REFIN/GAIN V nom
AGND + 100 mV
AV
DD
– 100 mV
AGND – 30 mV
AV
DD
+ 30 mV
±
1
±
5
±
125
±
2
100
100
90
V min
V max
V min
V max
nA max
pA/°C typ
nA/V typ
pA/V/°C typ
dB min
dB min
dB min
Absolute AIN Voltage Limits
Absolute AINCOM Voltage Limits
Analog Input Current
DC Input Current
2
DC Bias Current Drift
AINCOM Input Current
DC Input Current
2
DC Bias Current Drift
Normal-Mode Rejection
2
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
@ DC
REFIN Refers to Both REFIN1 and
REFIN2. REFIN = REFIN(+) –REFIN(–)
GAIN = 1 to 128
AIN1–AIN10 and AINCOM with
NEGBUF = 1
NEGBUF = 0
AIN1–AIN10 and AINCOM with NEGBUF = 1
NEGBUF = 0
±
2.56 V Range
50 Hz
±
1 Hz, SF Word = 82
60 Hz
±
1 Hz, SF Word = 68
100 dB typ, Analog Input = 1 V,
Input Range =
±
2.56 V
110 dB typ on
±
20 mV Range
50 Hz
±
1 Hz, SF Word = 82
60 Hz
±
1 Hz, SF Word = 68
REFIN Refers to Both REFIN1 and REFIN2
@ 50 Hz
@ 60 Hz
100
100
dB typ
dB typ
V nom
V min
V max
V min
V max
µA/V
typ
nA/V/°C typ
dB min
dB min
dB typ
dB typ
dB typ
REFERENCE INPUTS (REFIN1 AND REFIN2)
REFIN(+) to REFIN(–) Voltage
2.5
2
1
REFIN(+) to REFIN(–) Range
AV
DD
REFIN Common-Mode Range
AGND – 30 mV
AV
DD
+ 30 mV
Reference DC Input Current
0.5
Reference DC Input Current Drift
±
0.1
Normal-Mode Rejection
2
@ 50 Hz
100
@ 60 Hz
100
Common-Mode Rejection
@ DC
100
@ 50 Hz
100
@ 60 Hz
100
50 Hz
±
1 Hz, SF Word = 82
60 Hz
±
1 Hz, SF Word = 68
Input Range =
±
2.56 V
Analog Input = 1 V. Input Range =
±
2.56 V
REV. 0
–3–
(AV =
4.75 to 5.25 V,
AD7718–SPECIFICATIONS
32.768 kHz2.7 V to 3.6 V orBuffer VEnabled. AllDV = 2.7 V to T3.6 VtoorT 4.75 V to 5.25 V, REFIN(+) =
2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 =
Crystal Input
specifications
unless otherwise noted.)
DD
DD
MIN
MAX
1
Parameter
AD7718 (CHOP ENABLED)
Output Update Rate
No Missing Codes
2
Resolution
Output Noise and Update Rates
Integral Nonlinearity
Offset Error
3
Offset Error Drift vs. Temp
4
Full-Scale Error
3
Gain Drift vs. Temp
4
ANALOG INPUTS
Differential Input Full-Scale Voltage
B Grade
5.4
105
24
13
18
See Tables in
ADC Description
±
10
±
3
10
±
10
±
0.5
±1.024 ×
REFIN/GAIN
±
2
AGND + 100 mV
AV
DD
– 100 mV
AGND – 30 mV
AV
DD
+ 30 mV
±
1
±
5
±
125
±
2
100
100
90
Unit
Hz min
Hz max
Bits min
Bits p-p
Bits p-p
Test Conditions
CHOP
= 0
20 Hz Update Rate
±
20 mV Range, 20 Hz Update Rate
±
2.56 V Range, 20 Hz Update Rate
2 ppm Typical
ppm of FSR max
µV
typ
nV/°C typ
µV/°C
typ
ppm/°C typ
V nom
µV
typ
V min
V max
V min
V max
Range Matching
Absolute AIN Voltage Limits
Absolute AINCOM Voltage Limits
Analog Input Current
DC Input Current
2
DC Input Current Drift
AINCOM Input Current
DC Input Current
2
DC Bias Current Drift
Normal-Mode Rejection
2
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
@ DC
@ 50 Hz
2
@ 60 Hz
2
REFERENCE INPUTS (REFIN1 AND REFIN2)
REFIN(+) to REFIN(–) Voltage
REFIN(+) to REFIN(–) Range
2
REFIN Common-Mode Range
Reference DC Input Current
2
Reference DC Input Current Drift
Normal-Mode Rejection
2
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
2
@ DC
@ 50 Hz
@ 60 Hz
LOGIC INPUTS
5
All Inputs Except SCLK and XTAL1
2
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
REFIN Refers to Both REFIN1 and
REFIN2. REFIN = REFIN(+) REFIN(–)
GAIN = 1 to 128
Analog Input = 18 mV
AIN1–AIN10 and AINCOM with
NEGBUF = 1
NEGBUF = 0
AIN1–AIN10 and AINCOM with
NEGBUF = 1
nA max
pA/°C typ
nA/V typ
pA/V/°C typ
dB min
dB min
dB min
NEGBUF = 0
±
2.56 V Range
50 Hz
±
1 Hz, SF Word = 82
60 Hz
±
1 Hz, SF Word = 68
100 dB typ, Analog Input = 1 V,
Input Range =
±2.56
V
110 dB typ on
±
20 mV Range
50 Hz
±
1 Hz, 20 Hz Update Rate
60 Hz
±
1 Hz, 20 Hz Update Rate
REFIN Refers to Both REFIN1 and
REFIN2
100
100
2.5
1
AV
DD
AGND – 30 mV
AV
DD
+ 30 mV
±
0.5
±
0.01
100
100
110
110
110
dB min
dB min
V nom
V min
V max
V min
V max
µA/V
typ
nA/V/°C typ
dB min
dB min
dB typ
dB typ
dB typ
50 Hz
±
1 Hz, SF Word = 82
60 Hz
±
1 Hz, SF Word = 68
Input Range =
±
2.56 V
Analog Input = 1 V
50 Hz
±
1 Hz, 20 Hz Update Rate
60 Hz
±
1 Hz, 20 Hz Update Rate
0.8
0.4
2.0
V max
V max
V min
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V or 5 V
–4–
REV. 0
AD7708/AD7718
Parameter
LOGIC INPUTS (Continued)
SCLK Only (Schmitt-Triggered Input)
2
V
T(+)
V
T(–)
V
T(+)
– V
T(–)
V
T(+)
V
T(–)
V
T(+)
–V
T(–)
XTAL1 Only
2
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
Input Currents
B Grade
Unit
Test Conditions
1.4/2
0.8/1.4
0.3/0.85
0.95/2
0.4/1.1
0.3/0.85
0.8
3.5
0.4
2.5
±
10
–70
10
DV
DD
– 0.6
0.4
4
0.4
±
10
±
10
Binary
Offset Binary
1.05
×
FS
–1.05
×
FS
0.8
×
FS
2.1
×
FS
300
1
300
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V max
V min
V max
V min
µA
max
µA
max
pF typ
V min
V max
V min
V max
µA
max
pF typ
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V
DV
DD
= 3 V
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V
Logic Input = DV
DD
Logic Input = DGND, Typical –40
µA
@ 5 V
and –20
µA
at 3 V
All Digital Inputs
DV
DD
= 3 V, I
SOURCE
= 100
µA
DV
DD
= 3 V, I
SINK
= 100
µA
DV
DD
= 5 V, I
SOURCE
= 200
µA
DV
DD
= 5 V, I
SINK
= 1.6 mA
Input Capacitance
LOGIC OUTPUTS (Excluding XTAL2)
5
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
START-UP TIME
From Power-On
From Power-Down Mode
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
–AGND
DV
DD
–DGND
DI
DD
(Normal Mode)
AI
DD
(Normal Mode)
DI
DD
(Power-Down Mode)
Unipolar Mode
Bipolar Mode
V max
V min
V min
V max
ms typ
ms typ
ms typ
Oscillator Enabled
Oscillator Powered Down
AI
DD
(Power-Down Mode)
Power Supply Rejection (PSR)
Chop Disabled
Chop Enabled
AV
DD
and DV
DD
can be operated independently of each other.
2.7/3.6
V min/max
AV
DD
= 3 V nom
4.75/5.25
V min/max
AV
DD
= 5 V nom
2.7/3.6
V min/max
DV
DD
= 3 V nom
4.75/5.25
V min
DV
DD
= 5 V nom
0.55
mA max
DV
DD
= 3 V, 0.43 mA typ
0.65
mA max
DV
DD
= 5 V, 0.5 mA typ
1.1
mA max
AV
DD
= 3 V or 5 V, 0.85 mA typ
10
µA
max
DV
DD
= 3 V, 32.768 kHz Osc. Running
2
µA
max
DV
DD
= 3 V, Oscillator Powered Down
30
µA
max
DV
DD
= 5 V, 32.768 kHz Osc. Running
8
µA
max
DV
DD
= 5 V, Oscillator Powered Down
1
µA
max
AV
DD
= 3 V or 5 V
Input Range =
±
2.56 V, AIN = 1 V
70
dB min
95 dB typ
100
dB typ
NOTES
1
Temperature range is –40°C to +85°C.
2
Not production tested, guaranteed by design and/or characterization data at release.
3
Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error.
4
Recalibration at any temperature will remove these errors.
5
I/O Port Logic Levels are with respect to AV
DD
and AGND.
Specifications are subject to change without notice.
REV. 0
–5–
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