8Gb: x16, x32 GDDR5 SGRAM
Features
GDDR5 SGRAM
MT51J256M32 – 16 Meg x 32 I/O x 16 banks, 32 Meg x 16 I/O x 16 banks
Features
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V
DD
= V
DDQ
= 1.5V ±3% and 1.35V ±3%
Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s
16 internal banks
Four bank groups for
t
CCDL = 3
t
CK
8n-bit prefetch architecture: 256-bit per array read
or write access for x32; 128-bit for x16
Burst length (BL): 8 only
Programmable CAS latency: 7–24
Programmable WRITE latency: 4–7
Programmable CRC READ latency: 2–3
Programmable CRC WRITE latency: 8–14
Programmable EDC hold pattern for CDR
Precharge: Auto option for each burst access
Auto refresh and self refresh modes
Refresh cycles: 16,384 cycles/32ms
Interface: Pseudo open drain (POD-15) compatible
outputs: 40Ω pull-down, 60Ω pull-up
On-die termination (ODT): 60Ω or 120Ω (NOM)
ODT and output driver strength auto calibration
with external resistor ZQ pin: 120Ω
Programmable termination and driver strength off-
sets
Selectable external or internal V
REF
for data inputs;
programmable offsets for internal V
REF
Separate external V
REF
for address/command
inputs
x32/x16 mode configuration set at power-up with
EDC pin
Single-ended interface for data, address, and
command
Quarter data rate differential clock inputs CK_t,
CK_c for address and commands
Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes
(DQ, DBI_n, EDC)
DDR data (WCK) and addressing (CK)
SDR command (CK)
Write data mask function via address bus (single/
double byte mask)
Data bus inversion (DBI) and address bus inversion
(ABI)
Digital RAS lockout
• Address training: Address input monitoring via DQ
pins
• WCK2CK clock training: Phase information via EDC
pins
• Data read and write training via read FIFO (FIFO
depth = 6)
• Read FIFO pattern preloaded by LDFF command
• Direct write data load to read FIFO by WRTR com-
mand
• Consecutive read of read FIFO by RDTR command
• Read/write data transmission integrity secured by
cyclic redundancy check (CRC-8)
• Read/write EDC on/off mode
• Low power modes
• RDQS mode on EDC pin
• On-die temperature sensor with readout
• Automatic temperature sensor controlled self
refresh rate
• Vendor ID, FIFO depth and density info fields for
identification
• Mirror function with MF pin
• Boundary scan function with SEN pin
• Lead-free (RoHS-compliant) and halogen-free
packaging
• T
C
= 0°C to +95°C
Options
1
• Organization
– 256 Meg x 32 (words x bits)
• FBGA package
– 170-ball (12mm x 14mm)
• Timing – maximum data rate
– 6.0 Gb/s, 5.0 Gb/s
– 7.0 Gb/s, 6.0 Gb/s
– 8.0 Gb/s, 6.0 Gb/s
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
256M32
HF
-60
-70
-80
None
A
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
09005aef86281891
8Gb_gddr5_sgram_brief.pdf - Rev. F 2/17 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5 SGRAM
Features
Figure 1: Part Numbering
MT51J 256M32 HF -80 : A
Micron Memory
Configuration
256M32 = 256 Meg x 32
Package
HF = 170-ball 12.00mm x 14.00mm FBGA
Revision A
Temperature
: = Commercial
Data Rate
-80 = 8.0 Gb/s
-70 = 7.0 Gb/s
-60 = 6.0 Gb/s
Note:
1. This Micron GDDR5 SGRAM is available in different speed bins. The operating range and AC timings of a
faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a
drop-in replacement of a slower bin device when operated within the supply voltage and frequency range
of the slower bin device.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site:
http://www.micron.com.
09005aef86281891
8Gb_gddr5_sgram_brief.pdf - Rev. F 2/17 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 2: 170-Ball FBGA – MF = 0 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
MF
V
SS
V
DD
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
2
DQ1
DQ3
EDC0
DBI0_n
DQ5
DQ7
V
DDQ
V
SSQ
RESET_n
V
SSQ
V
DDQ
DQ31
DQ29
DBI3_n
EDC3
DQ27
DQ25
3
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
RAS_n
V
DDQ
CKE_n
V
DDQ
CAS_n
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
4
DQ0
DQ2
V
SSQ
5
NC
V
SS
V
DD
6
7
8
9
10
V
REFD
V
SS
V
DD
V
SS
V
DDQ
V
SSQ
V
SS
BA3, A3
SEN
BA1, A5
V
SS
V
SSQ
V
DDQ
V
SS
V
DD
V
SS
V
REFD
11
DQ8
DQ10
V
SSQ
V
DD
DQ12
DQ14
V
DD
BA0, A2
CK_c
BA2, A4
V
DD
DQ22
DQ20
V
DD
V
SSQ
DQ18
DQ16
12
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
CS_n
V
DDQ
CK_t
V
DDQ
WE_n
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
13
DQ9
DQ11
EDC1
DBI1_n
DQ13
DQ15
V
DDQ
V
SSQ
ZQ
V
SSQ
V
DDQ
DQ23
DQ21
DBI2_n
EDC2
DQ19
DQ17
14
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
V
REFC
V
SS
V
DD
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
WCK01_t WCK01_c
DQ4
DQ6
V
DD
A10, A0
ABI_n
A8, A7
V
DD
DQ30
DQ28
V
DDQ
V
SSQ
V
SS
A9, A1
A12, A13
A11, A6
V
SS
V
SSQ
V
DDQ
WCK23_t WCK23_c
V
SSQ
DQ26
DQ24
V
DD
V
SS
NC
(Top view)
Data
Addresses
GDDR5
Supply
Ground
Note:
1. Balls shown with a heavy, solid outline are off in x16 mode.
09005aef86281891
8Gb_gddr5_sgram_brief.pdf - Rev. F 2/17 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
Figure 3: 170-Ball FBGA – MF = 1 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
MF
V
SS
V
DD
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
2
DQ25
DQ27
EDC3
DBI3_n
DQ29
DQ31
V
DDQ
V
SSQ
RESET_n
V
SSQ
V
DDQ
DQ7
DQ5
DBI0_n
EDC0
DQ3
DQ1
3
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
CAS_n
V
DDQ
CKE_n
V
DDQ
RAS_n
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
4
DQ24
DQ26
V
SSQ
5
NC
V
SS
V
DD
6
7
8
9
10
V
REFD
V
SS
V
DD
V
SS
V
DDQ
V
SSQ
V
SS
BA1, A5
SEN
BA3, A3
V
SS
V
SSQ
V
DDQ
V
SS
V
DD
V
SS
V
REFD
11
DQ16
DQ18
V
SSQ
V
DD
DQ20
DQ22
V
DD
BA2, A4
CK_c
BA0, A2
V
DD
DQ14
DQ12
V
DD
V
SSQ
DQ10
DQ8
12
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
WE_n
V
DDQ
CK_t
V
DDQ
CS_n
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
13
DQ17
DQ19
EDC2
DBI2_n
DQ21
DQ23
V
DDQ
V
SSQ
ZQ
V
SSQ
V
DDQ
DQ15
DQ13
DBI1_n
EDC1
DQ11
DQ9
14
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
V
REFC
V
SS
V
DD
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
WCK23_t WCK23_c
DQ28
DQ30
V
DD
A8, A7
ABI_n
A10, A0
V
DD
DQ6
DQ4
V
DDQ
V
SSQ
V
SS
A11, A6
A12, A13
A9, A1
V
SS
V
SSQ
V
DDQ
WCK01_t WCK01_c
V
SSQ
DQ2
DQ0
V
DD
V
SS
NC
(Top view)
Data
Addresses
GDDR5
Supply
Ground
Note:
1. Balls shown with a heavy, solid outline are off in x16 mode.
09005aef86281891
8Gb_gddr5_sgram_brief.pdf - Rev. F 2/17 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
Table 1: 170-Ball FBGA Ball Descriptions
Symbol
A[13:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands. A[6:0] (A7) provide
the column address and A8 defines the auto precharge bit for READ/WRITE com-
mands, to select one location out of the memory array in the respective bank. A8
sampled during a PRECHARGE command determines whether the PRECHARGE ap-
plies to one bank (A8 LOW, bank selected by BA[3:0]) or all banks (A8 HIGH). The ad-
dress inputs also provide the op-code during a MODE REGISTER SET command and
the data bits during LDFF commands. A[12:8] are sampled with the rising edge of
CK_t and A[7:0], A13 are sampled with the rising edge of CK_c.
Address bus inversion:
Reduces the power requirements on address pins by limit-
ing the number of address lines driving LOW to 5. ABI_n is enabled by the corre-
sponding ABI mode register bit.
Bank address inputs:
Define the bank to which an ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[3:0] define which mode register is loaded
during the MODE REGISTER SET command. BA[3:0] are sampled with the rising edge
of CK_t.
Clock:
CK_t and CK_c are differential clock inputs. Command inputs are latched on
the rising edge of CK_t. Address inputs are latched on the rising edge of CK_t and
the rising edge of CK_c. All latencies are referenced to CK_t. CK_t and CK_c are ex-
ternally terminated.
Data Clocks:
WCK_t and WCK_c are differential clocks used for write data capture
and read data output. WCK01_t and WCK01_c are associated with DQ[15:0], DBI0_n,
DBI1_n, EDC0, and EDC1. WCK23_t and WCK23_c are associated with DQ[31:16],
DBI2_n, DBI3_n, EDC2, and EDC3. WCK clocks operate at nominally twice the CK
clock frequency.
Clock enable:
CKE_n enables (registered LOW) and disables (registered HIGH) inter-
nal circuitry and clocks on the device. The specific circuitry that is enabled/disabled is
dependent upon the device configuration and operating mode. Taking CKE_n HIGH
provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or active power-down (row active in any bank). CKE_n is synchronous for power-
down entry and exit and for self refresh entry. CKE_n must be maintained LOW
throughout read and write accesses. Input buffers (excluding CKE_n) are disabled
during SELF REFRESH operation. The value of CKE_n latched at power-up with RE-
SET_n going HIGH determines the termination value of the address and command
inputs.
Chip select:
CS_n enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS_n is registered HIGH, but in-
ternal command execution continues. CS_n is considered part of the command code.
Mirror function:
V
DDQ
CMOS input. Must be tied to V
DDQ
or V
SS
.
Command inputs:
RAS_n, CAS_n, and WE_n (along with CS_n) define the com-
mand being entered.
Reset:
RESET_n is an active LOW CMOS input referenced to V
SS
. A full chip reset may
be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are
disabled.
Scan enable:
V
DDQ
CMOS input. Must be tied to V
SS
when not in use.
ABI_n
Input
BA[3:0]
Input
CK_t, CK_c
Input
WCK01_t, WCK01_c/
WCK23_t, WCK23_c
Input
CKE_n
Input
CS_n
Input
MF
RAS_n, CAS_n, WE_n
RESET_n
Input
Input
Input
SEN
Input
09005aef86281891
8Gb_gddr5_sgram_brief.pdf - Rev. F 2/17 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
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