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10 Core Fabric and
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A10-HANDBOOK | 2018.08.28
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1. Logic Array Blocks and Adaptive Logic Modules in Intel
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10 Devices................... 7
1.1. LAB..................................................................................................................... 7
1.1.1. MLAB....................................................................................................... 8
1.1.2. Local and Direct Link Interconnects ............................................................. 9
1.1.3. Shared Arithmetic Chain and Carry Chain Interconnects ............................... 10
1.1.4. LAB Control Signals..................................................................................11
1.1.5. ALM Resources ....................................................................................... 12
1.1.6. ALM Output ............................................................................................13
1.2. ALM Operating Modes .......................................................................................... 14
1.2.1. Normal Mode ..........................................................................................14
1.2.2. Extended LUT Mode..................................................................................17
1.2.3. Arithmetic Mode ..................................................................................... 18
1.2.4. Shared Arithmetic Mode ...........................................................................20
1.3. LAB Power Management Techniques ...................................................................... 21
1.4. Logic Array Blocks and Adaptive Logic Modules in Intel Arria 10 Devices Revision
History............................................................................................................ 21
2. Embedded Memory Blocks in Intel Arria 10 Devices......................................................22
2.1. Types of Embedded Memory.................................................................................. 22
2.1.1. Embedded Memory Capacity in Intel Arria 10 Devices................................... 23
2.2. Embedded Memory Design Guidelines for Intel Arria 10 Devices................................. 23
2.2.1. Consider the Memory Block Selection..........................................................23
2.2.2. Guideline: Implement External Conflict Resolution........................................ 24
2.2.3. Guideline: Customize Read-During-Write Behavior........................................24
2.2.4. Guideline: Consider Power-Up State and Memory Initialization....................... 27
2.2.5. Guideline: Control Clocking to Reduce Power Consumption............................ 28
2.3. Embedded Memory Features................................................................................. 28
2.4. Embedded Memory Modes.....................................................................................29
2.4.1. Embedded Memory Configurations for Single-port Mode................................ 30
2.4.2. Embedded Memory Configurations for Dual-port Modes................................. 31
2.5. Embedded Memory Clocking Modes........................................................................ 32
2.5.1. Clocking Modes for Each Memory Mode....................................................... 32
2.5.2. Asynchronous Clears in Clocking Modes...................................................... 33
2.5.3. Output Read Data in Simultaneous Read/Write.............................................33
2.5.4. Independent Clock Enables in Clocking Modes..............................................33
2.6. Parity Bit in Embedded Memory Blocks....................................................................33
2.7. Byte Enable in Embedded Memory Blocks................................................................33
2.7.1. Byte Enable Controls in Memory Blocks....................................................... 34
2.7.2. Data Byte Output.....................................................................................34
2.7.3. RAM Blocks Operations............................................................................. 34
2.8. Memory Blocks Packed Mode Support..................................................................... 35
2.9. Memory Blocks Address Clock Enable Support..........................................................35
2.10. Memory Blocks Asynchronous Clear...................................................................... 36
2.11. Memory Blocks Error Correction Code Support....................................................... 37
2.11.1. Error Correction Code Truth Table............................................................. 38
2.12. Embedded Memory Blocks in Intel Arria 10 Devices Revision History......................... 38
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3. Variable Precision DSP Blocks in Intel Arria 10 Devices................................................ 40
3.1. Supported Operational Modes in Intel Arria 10 Devices............................................. 40
3.1.1. Features................................................................................................. 42
3.2. Resources........................................................................................................... 43
3.3. Design Considerations.......................................................................................... 44
3.3.1. Operational Modes................................................................................... 45
3.3.2. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic......................... 46
3.3.3. Accumulator for Fixed-Point Arithmetic....................................................... 46
3.3.4. Chainout Adder........................................................................................46
3.4. Block Architecture................................................................................................46
3.4.1. Input Register Bank................................................................................. 48
3.4.2. Pipeline Register...................................................................................... 51
3.4.3. Pre-Adder for Fixed-Point Arithmetic........................................................... 52
3.4.4. Internal Coefficient for Fixed-Point Arithmetic.............................................. 52
3.4.5. Multipliers............................................................................................... 52
3.4.6. Adder..................................................................................................... 52
3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic........................... 53
3.4.8. Systolic Registers for Fixed-Point Arithmetic................................................ 53
3.4.9. Double Accumulation Register for Fixed-Point Arithmetic............................... 54
3.4.10. Output Register Bank..............................................................................54
3.5. Operational Mode Descriptions...............................................................................54
3.5.1. Operational Modes for Fixed-Point Arithmetic............................................... 55
3.5.2. Operational Modes for Floating-Point Arithmetic........................................... 61
3.6. Variable Precision DSP Blocks in Intel Arria 10 Devices Revision History.......................68
4. Clock Networks and PLLs in Intel Arria 10 Devices....................................................... 70
4.1. Clock Networks....................................................................................................70
4.1.1. Clock Resources in Intel Arria 10 Devices.................................................... 71
4.1.2. Hierarchical Clock Networks.......................................................................73
4.1.3. Types of Clock Networks........................................................................... 75
4.1.4. Clock Network Sources............................................................................. 78
4.1.5. Clock Control Block.................................................................................. 79
4.1.6. Clock Power Down....................................................................................82
4.1.7. Clock Enable Signals................................................................................ 82
4.2. Intel Arria 10 PLLs............................................................................................... 83
4.2.1. PLL Usage............................................................................................... 85
4.2.2. PLL Architecture.......................................................................................85
4.2.3. PLL Control Signals.................................................................................. 86
4.2.4. Clock Feedback Modes.............................................................................. 86
4.2.5. Clock Multiplication and Division.................................................................87
4.2.6. Programmable Phase Shift........................................................................ 88
4.2.7. Programmable Duty Cycle......................................................................... 89
4.2.8. PLL Cascading......................................................................................... 89
4.2.9. Reference Clock Sources........................................................................... 90
4.2.10. Clock Switchover....................................................................................90
4.2.11. PLL Reconfiguration and Dynamic Phase Shift.............................................96
4.3. Clock Networks and PLLs in Intel Arria 10 Devices Revision History.............................96
5. I/O and High Speed I/O in Intel Arria 10 Devices.........................................................99
5.1. I/O and Differential I/O Buffers in Intel Arria 10 Devices..........................................100
5.2. I/O Standards and Voltage Levels in Intel Arria 10 Devices...................................... 101
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5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
6.1.
6.2.
6.3.
6.4.
5.2.1. I/O Standards Support for FPGA I/O in Intel Arria 10 Devices.......................101
5.2.2. I/O Standards Support for HPS I/O in Intel Arria 10 Devices........................ 102
5.2.3. I/O Standards Voltage Levels in Intel Arria 10 Devices................................ 102
Intel FPGA I/O IP Cores for Intel Arria 10 Devices...................................................104
I/O Resources in Intel Arria 10 Devices................................................................. 105
5.4.1. GPIO Banks, SERDES, and DPA Locations in Intel Arria 10 Devices................105
5.4.2. GPIO Buffers and LVDS Channels in Intel Arria 10 Devices........................... 110
5.4.3. I/O Banks Groups in Intel Arria 10 Devices................................................ 113
5.4.4. I/O Vertical Migration for Intel Arria 10 Devices.......................................... 119
Architecture and General Features of I/Os in Intel Arria 10 Devices...........................120
5.5.1. I/O Element Structure in Intel Arria 10 Devices.......................................... 120
5.5.2. Features of I/O Pins in Intel Arria 10 Devices............................................. 122
5.5.3. Programmable IOE Features in Intel Arria 10 Devices.................................. 123
5.5.4. On-Chip I/O Termination in Intel Arria 10 Devices.......................................129
5.5.5. External I/O Termination for Intel Arria 10 Devices..................................... 139
High Speed Source-Synchronous SERDES and DPA in Intel Arria 10 Devices.............. 147
5.6.1. SERDES Circuitry................................................................................... 148
5.6.2. SERDES I/O Standards Support in Intel Arria 10 Devices............................. 149
5.6.3. Differential Transmitter in Intel Arria 10 Devices.........................................151
5.6.4. Differential Receiver in Intel Arria 10 Devices............................................. 153
5.6.5. PLLs and Clocking for Intel Arria 10 Devices...............................................161
5.6.6. Timing and Optimization for Intel Arria 10 Devices......................................172
Using the I/Os and High Speed I/Os in Intel Arria 10 Devices................................... 177
5.7.1. I/O and High-Speed I/O General Guidelines for Intel Arria 10 Devices........... 177
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards......... 179
5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During
Power Sequencing.................................................................................. 180
5.7.4. Guideline: Using the I/O Pins in HPS Shared I/O Banks............................... 180
5.7.5. Guideline: Maximum DC Current Restrictions............................................. 181
5.7.6. Guideline: Intel FPGA LVDS SERDES IP Core Instantiation........................... 181
5.7.7. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode................................. 182
5.7.8. Guideline: Minimizing High Jitter Impact on Intel Arria 10 GPIO Performance. 182
5.7.9. Guideline: Usage of I/O Bank 2A for External Memory Interfaces.................. 183
I/O and High Speed I/O in Intel Arria 10 Devices Revision History.............................184
6. External Memory Interfaces in Intel Arria 10 Devices................................................. 189
Key Features of the Intel Arria 10 External Memory Interface Solution.......................189
Memory Standards Supported by Intel Arria 10 Devices.......................................... 190
External Memory Interface Widths in Intel Arria 10 Devices..................................... 191
External Memory Interface I/O Pins in Intel Arria 10 Devices....................................192
6.4.1. Guideline: Usage of I/O Bank 2A for External Memory Interfaces.................. 192
6.5. Memory Interfaces Support in Intel Arria 10 Device Packages.................................. 193
6.5.1. Intel Arria 10 Package Support for DDR3 x40 with ECC...............................194
6.5.2. Intel Arria 10 Package Support for DDR3 x72 with ECC Single and Dual-Rank.196
6.5.3. Intel Arria 10 Package Support for DDR4 x40 with ECC................................198
6.5.4. Intel Arria 10 Package Support for DDR4 x72 with ECC Single-Rank.............. 200
6.5.5. Intel Arria 10 Package Support for DDR4 x72 with ECC Dual-Rank................ 202
6.5.6. HPS External Memory Interface Connections in Intel Arria 10....................... 203
6.6. External Memory Interface IP Support in Intel Arria 10 Devices................................ 207
6.6.1. Ping Pong PHY IP....................................................................................208
6.7. External Memory Interface Architecture of Intel Arria 10 Devices.............................. 209
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6.7.1. I/O Bank...............................................................................................209
6.7.2. I/O AUX................................................................................................ 219
6.8. External Memory Interface in Intel Arria 10 Devices Revision History.........................221
7. Configuration, Design Security, and Remote System Upgrades in Intel Arria 10
Devices.................................................................................................................. 223
7.1. Enhanced Configuration and Configuration via Protocol...........................................223
7.2. Configuration Schemes....................................................................................... 224
7.2.1. Active Serial Configuration.......................................................................225
7.2.2. Passive Serial Configuration..................................................................... 234
7.2.3. Fast Passive Parallel Configuration............................................................ 239
7.2.4. JTAG Configuration................................................................................. 243
7.3. Configuration Details.......................................................................................... 246
7.3.1. MSEL Pin Settings.................................................................................. 246
7.3.2. CLKUSR................................................................................................ 247
7.3.3. Configuration Sequence.......................................................................... 248
7.3.4. Configuration Timing Waveforms.............................................................. 251
7.3.5. Estimating Configuration Time................................................................. 254
7.3.6. Device Configuration Pins........................................................................ 255
7.3.7. Configuration Data Compression.............................................................. 258
7.4. Remote System Upgrades Using Active Serial Scheme.............................................259
7.4.1. Configuration Images............................................................................. 260
7.4.2. Configuration Sequence in the Remote Update Mode................................... 262
7.4.3. Remote System Upgrade Circuitry............................................................ 263
7.4.4. Enabling Remote System Upgrade Circuitry............................................... 263
7.4.5. Remote System Upgrade Registers........................................................... 264
7.4.6. Remote System Upgrade State Machine.................................................... 265
7.4.7. User Watchdog Timer..............................................................................265
7.5. Design Security................................................................................................. 266
7.5.1. Security Key Types................................................................................. 267
7.5.2. Security Modes...................................................................................... 268
7.5.3. Intel Arria 10 Qcrypt Security Tool............................................................ 269
7.5.4. Design Security Implementation Steps...................................................... 270
7.6. Configuration, Design Security, and Remote System Upgrades in Intel Arria 10
Devices Revision History...................................................................................271
8. SEU Mitigation for Intel Arria 10 Devices.................................................................... 274
8.1. Intel Arria 10 SEU Mitigation Overview..................................................................274
8.1.1. Mitigating Single Event Upset...................................................................274
8.2. Intel Arria 10 SEU Mitigation Techniques............................................................... 276
8.2.1. Mitigating SEU Effects in Configuration RAM............................................... 277
8.2.2. Mitigating SEU Effects in Embedded User RAM............................................286
8.2.3. Triple-Module Redundancy....................................................................... 287
8.2.4. Intel Quartus Prime Software SEU FIT Reports........................................... 288
8.3. CRAM Error Detection Settings Reference.............................................................. 292
8.4. Specifications.................................................................................................... 292
8.4.1. Error Detection Frequency....................................................................... 292
8.4.2. Error Detection Time.............................................................................. 293
8.4.3. EMR Update Interval...............................................................................293
8.4.4. Error Correction Time............................................................................. 295
8.5. SEU Mitigation for Intel Arria 10 Devices Revision History........................................ 295
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