Programmable Fanout Buffer
5P1103
DATASHEET
Description
The 5P1103 is a programmable fanout buffer intended for
high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface.
The outputs are generated from a single reference clock. The
input reference can be crystal, external single-ended or
differential clock. The reference clock can come from one of
the two redundant clock inputs and is selected by CLKSEL
pin. A glitchless manual switchover function allows one of the
redundant clocks to be selected during normal operation. See
reference clock input section for details.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two
addresses to allow multiple devices to be used in a system.
I
2
C
Features
•
Up to two high performance universal differential output
pairs
– Low RMS additive phase jitter: 0.2ps
•
Four banks of internal non-volatile in-system
•
•
•
programmable or factory programmable OTP memory
I
2
C serial programming interface
One additional LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
•
I/O Standards:
•
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Pin Assignment
OUT0_SEL_I2CB
•
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
•
•
•
•
•
•
•
V
DDO
2
OUT2
OUT2B
V
DDA
NC
NC
each output pair
Redundant clock inputs with manual switchover
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
CLKSEL
1
2
3
4
5
6
24 23 22 21 20 19
18
17
EPAD
7
8
9
13
10 11 12
SEL1/SDA
SEL0/SCL
SD/OE
V
DDA
NC
24-pin VFQFPN
5P1103 REVISION D 07/13/15
1
©2015 Integrated Device Technology, Inc.
NC
OUT1B
16
15
14
V
DDO
0
V
DDO
1
OUT1
V
DDD
5P1103 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
V
DDO
0
OUT0_SEL_I2CB
V
DDO
1
CLKIN
CLKINB
V
DDO
2
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
OTP
and
Control Logic
OUT1
OUT1B
OUT2
OUT2B
V
DDA
V
DDA
V
DDA
V
DDD
Applications
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
PROGRAMMABLE FANOUT BUFFER
2
REVISION D 07/13/15
5P1103 DATASHEET
Table 1:Pin Descriptions
Number
1
2
3
4
5
Name
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
Input
Input
Input
Input
Power
Type
Pull-down
Pull-down
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Input clock select. Selects the active input reference source, when in Manual
switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
No connect.
No connect.
No connect.
No connect.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
Connect to ground pad.
6
CLKSEL
Input
Pull-down
7
SD/OE
Input
Pull-down
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SEL1/SDA
SEL0/SCL
VDDA
NC
NC
NC
NC
VDDA
OUT2B
OUT2
VDDO2
OUT1B
OUT1
VDDO1
VDDD
VDDO0
Input
Input
Power
Pull-down
Pull-down
Power
Output
Output
Power
Output
Output
Power
Power
Power
24
OUT0_SELB_I2C Input/Output
Pull-down
ePAD
VEE
Power
REVISION D 07/13/15
3
PROGRAMMABLE FANOUT BUFFER
5P1103 DATASHEET
Configuration and Input Descriptions
Table 2: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
OUT0_SEL_I2CB SEL1 SEL0
I
2
C
REG0:7 Config
@ POR
Access
1
1
1
1
0
0
0
0
1
1
X
X
0
1
0
1
X
X
No
No
No
No
Yes
Yes
0
0
0
0
1
0
0
1
2
3
I2C
defaults
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDD/VDDA.
The SELx pins must be driven with a digital signal of < 300nS
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Table 3: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I
2
C programming as
shown in Table 4.
PRIMSRC
0
0
1
1
CLKSEL
0
1
0
1
Source
XIN/REF
CLKIN, CLKINB
CLKIN, CLKINB
XIN/REF
PRIMSRC is bit 1 of Register 0x13.
PROGRAMMABLE FANOUT BUFFER
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REVISION D 07/13/15
5P1103 DATASHEET
Reference Clock Input Pins and
Selection
The 5P1103 supports up to two clock inputs. One input
supports a crystal between XIN and XOUT. XIN can also be
driven from a single ended reference clock. XIN can accept
small amplitude signals like from TCXO or one channel of a
differential clock.
The second clock input (CLKIN, CLKINB) is a fully differential
input that only accepts a reference clock. The differential input
accepts differential clocks from all the differential logic types
and can also be driven from a single ended clock on one of the
input pins.
The CLKSEL pin selects the input clock between either
XTAL/REF or (CLKIN, CLKINB).
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock. The non-primary clock is designated as the secondary
clock in case the primary clock goes absent and a backup is
needed. The PRIMSRC bit determines which clock input will
be selected as primary clock. When PRIMSRC bit is “0”,
XIN/REF is selected as the primary clock, and when “1”,
(CLKIN, CLKINB) as the primary clock.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits must be set to “0x” for
manual switchover which is detailed in Manual Switchover
Mode section.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits
6
Step (pF)
0.5
Min (pF)
9
Max (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
You can write the following equations for the total capacitance
at each crystal pin:
C
XIN
= Ci
1
+ Cs
1
+ Ce
1
C
XOUT
= Ci
2
+ Cs
2
+ Ce
2
Ci
1
and Ci
2
are the internal, tunable capacitors. Ci
1
and Cs
2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce
1
and Ce
2
are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce
1
and/or Ce
2
to avoid
crystal startup issues. Ce
1
and Ce
2
can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = C
XIN
× C
XOUT
/ (C
XIN
+ C
XOUT
)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
C
XIN
= C
XOUT
= Cx
→
CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
REVISION D 07/13/15
5
PROGRAMMABLE FANOUT BUFFER
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