Changes to Table 3 ............................................................................ 4
5/2016—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 3
Changes to Programmable Precision Enable Section ................ 16
Changes to Current-Limit and Thermal Shutdown Section .... 17
3/2016—Revision 0: Initial Version
Rev. B | Page 2 of 22
Data Sheet
SPECIFICATIONS
V
IN
= V
OUT
+ 0.5 V or 2.3 V, whichever is greater; V
EN
= V
IN
; I
LOAD
= 10 mA; C
IN
= C
OUT
= 10 µF; C
REG
= C
REF
= C
BYP
= 1 µF;
T
A
= 25°C for typical specifications; T
A
= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
NOISE
1
Output Noise
Noise Spectral Density
POWER SUPPLY REJECTION RATIO
1
Symbol
V
IN
I
LOAD
I
GND
I
IN_SD
OUT
NOISE
OUT
NSD
PSRR
Test Conditions/Comments
Min
2.3
Typ
ADP7156
I
LOAD
= 0 µA
I
LOAD
= 1.2 A
EN = GND
V
OUT
= 1.2 V to 3.3 V
10 Hz to 100 kHz
100 Hz to 100 kHz
10 kHz to 1 MHz
1 kHz to 100 kHz, V
IN
= 4.0 V, V
OUT
= 3.3 V,
I
LOAD
= 1.2 A
1 MHz, V
IN
= 4.0 V, V
OUT
= 3.3 V, I
LOAD
= 1.2 A
1 kHz to 100 kHz, V
IN
= 2.6 V, V
OUT
= 1.8 V,
I
LOAD
= 1.2 A
1 MHz, V
IN
= 2.6 V, V
OUT
= 1.8 V, I
LOAD
= 1.2 A
1.2
−0.6
−1.0
−1.5
−0.1
4.0
7.0
0.2
1.6
0.9
1.7
80
60
80
60
Max
5.5
1.2
8.0
12.0
4
Unit
V
A
mA
mA
µA
µV rms
µV rms
nV/√Hz
dB
dB
dB
dB
OUTPUT VOLTAGE ACCURACY
Output Voltage
2
Initial Accuracy
V
OUT
I
LOAD
= 10 mA, T
A
= 25°C
10 mA < I
LOAD
< 1.2 A, T
A
= 25°C
10 mA < I
LOAD
< 1.2 A, T
A
= −40°C to +125°C
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
I
LIMIT
V
IN
= V
OUT
+ 0.5 V or 2.3 V, whichever is greater
to 5.5 V
I
OUT
= 10 mA to 1.2 A
3.3
+0.6
+1.0
+1.5
+0.1
0.3
22
1.8
60
120
650
31
850
650
1.2
0.6
0.5
V
%
%
%
%/V
%/A
mA
A
mV
mV
Ω
kΩ
Ω
Ω
ms
ms
ms
°C
°C
REGULATION
Line
Load
3
CURRENT-LIMIT THRESHOLD
4
REF
VOUT
DROPOUT VOLTAGE
5
PULL-DOWN RESISTANCE
VOUT
VREG
REF
BYP
START-UP TIME
1, 6
VOUT
VREG
REF
THERMAL SHUTDOWN
1
Threshold
Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
1.4
V
DROPOUT
I
OUT
= 600 mA, V
OUT
= 3.3 V
I
OUT
= 1.2 A, V
OUT
= 3.3 V
EN = 0 V, V
IN
= 5.5 V
V
OUT
= 1 V
V
REG
= 1 V
V
REF
= 1 V
V
BYP
= 1 V
V
OUT
= 3.3 V
2.4
80
170
V
OUT_PULL
V
REG_PULL
V
REF_PULL
V
BYP_PULL
t
START-UP
t
REG_START-UP
t
REF_START-UP
TS
SD
TS
SD_HYS
T
J
rising
150
15
UVLO
RISE
UVLO
FALL
UVLO
HYS
1.95
2.22
2.02
200
2.29
V
V
mV
Rev. B | Page 3 of 22
ADP7156
Parameter
VREG UVLO THRESHOLDS
7
Rising
Falling
Hysteresis
EN INPUT PRECISION
EN Input
Logic High
Logic Low
Logic Hysteresis
LEAKAGE CURRENT
REF_SENSE
EN
1
2
Data Sheet
Symbol
VREGUVLO
RISE
VREGUVLO
FALL
VREGUVLO
HYS
2.3 V ≤ V
IN
≤ 5.5 V
V
EN_HIGH
V
EN_LOW
V
EN_HYS
I
REF_SENSE_LKG
I
EN_LKG
1.13
1.05
1.22
1.13
90
10
0.01
1.31
1.22
V
V
mV
nA
µA
Test Conditions/Comments
Min
Typ
Max
1.94
1.60
185
Unit
V
V
mV
EN = V
IN
or GND
1
Guaranteed by characterization; not production tested.
The
ADP7156
is available in 16 standard voltages between 1.2 V and 3.3 V, including 1.2 V, 1.3 V, 1.5 V, 1.6 V, 1.8 V, 2.0 V, 2.2 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V,
3.2 V, and 3.3 V.
3
Based on an endpoint calculation using 10 mA and 1.2 A loads.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
5
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for
output voltages greater than 2.3 V.
6
Start-up time is defined as the time between the rising edge of V
EN
to V
OUT
, V
REG
, or V
REF
being at 90% of its nominal value.
7
The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
MINIMUM CAPACITANCE
Input
1
Regulator
Output
1
Bypass
Reference
CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR)
C
OUT
, C
IN
C
REG
, C
REF
C
BYP
1
Symbol
C
IN
C
REG
C
OUT
C
BYP
C
REF
Test Conditions/Comments
T
A
= −40°C to +125°C
Min
7.0
0.7
7.0
0.1
0.7
Typ
10.0
1.0
10.0
1.0
1.0
Max
Unit
µF
µF
µF
µF
µF
T
A
= −40°C to +125°C
R
ESR
R
ESR
R
ESR
0.1
0.2
2.0
Ω
Ω
Ω
The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any low dropout regulator.
Rev. B | Page 4 of 22
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to Ground
VREG to Ground
VOUT to Ground
VOUT_SENSE to Ground
VOUT to VOUT_SENSE
BYP to VOUT
EN to Ground
BYP to Ground
REF to Ground
REF_SENSE to Ground
Storage Temperature Range
Operational Junction Temperature
Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to V
IN
, or +4 V
(whichever is less)
−0.3 V to V
REG
, or +4 V
(whichever is less)
−0.3 V to V
REG
, or +4 V
(whichever is less)
±0.3 V
±0.3 V
−0.3 V to +7 V
−0.3 V to V
REG
, or +4 V
(whichever is less)
−0.3 V to V
REG
, or +4 V
(whichever is less)
−0.3 V to +4 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
ADP7156
Junction to ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
Ψ
JB
is the junction to board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a 4-layer board. JESD51-12,
Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. Ψ
JB
measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ
JB
. Therefore, Ψ
JB
thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make Ψ
JB
more useful in real-world
applications. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
) using
the following formula:
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
JB
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The
ADP7156
can be damaged when the junction
temperature limits are exceeded. Monitoring ambient tempera-
ture does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (T
J
) of the device is dependent on the
ambient temperature (T
A
), the power dissipation of the device
(P
D
), and the junction to ambient thermal resistance of the
package (θ
JA
).
Calculate the maximum junction temperature (T
J
) from the
ambient temperature (T
A
) and power dissipation (P
D
) using
the following formula:
T
J
=
T
A
+ (P
D
×
θ
JA
)
THERMAL RESISTANCE
θ
JA
, θ
JC
, and Ψ
JB
are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
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