SY100E137JC datasheet, PDF - EEWORLD Datasheet

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SY100E137JC: Description8-BIT RIPPLE COUNTER; File Size65KB，5 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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SY100E137JC Overview

8-BIT RIPPLE COUNTER

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Micrel, Inc.

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

SY10E137

SY100E137

FEATURES

1.8GHz min. count frequency

Extended 100E V

range of –4.2V to –5.5V

Synchronous and asynchronous enable pins

Differential clock input and data output pins

output for single-ended use

Asynchronous Master Reset

DESCRIPTION

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN

and EN

, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN

(or EN

)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

The E137 can also be driven single-endedly utilizing

the V

output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the V

pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. V

can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Internal 75K

Ω

input pull-down resistors

Available in 28-pin PLCC packge

PIN NAMES

CLK, CLK

–Q

, Q

–Q

A_Start

, EN

CCO

Function

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

to Output

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: E

Amendment: /0

Issue Date: March 2006

SY100E137JC Related Products

	SY100E137JC	SY100E137	SY10E137	SY10E137JC	SY10E137_06	SY10E137JZTR	SY10E137JCTR	SY100E137JZTR	SY100E137JCTR
Description	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER	8-BIT RIPPLE COUNTER
Is it Rohs certified?	-	-	-	incompatible	-	conform to	incompatible	conform to	incompatible
Maker	-	-	-	Microchip	-	Microchip	Microchip	Microchip	Microchip
package instruction	-	-	-	QCCJ, LDCC28,.5SQ	-	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Reach Compliance Code	-	-	-	_compli	-	compli	_compli	compli	_compli
Counting direction	-	-	-	UP	-	UP	UP	UP	UP
series	-	-	-	10E	-	10E	10E	100E	100E
JESD-30 code	-	-	-	S-PQCC-J28	-	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	-	-	-	e0	-	e3	e0	e3	e0
Load/preset input	-	-	-	NO	-	NO	NO	NO	NO
Logic integrated circuit type	-	-	-	BINARY COUNTER	-	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Maximum Frequency@Nom-Su	-	-	-	1800000000 Hz	-	1800000000 Hz	1800000000 Hz	1800000000 Hz	1800000000 Hz
Operating mode	-	-	-	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Number of digits	-	-	-	8	-	8	8	8	8
Number of functions	-	-	-	1	-	1	1	1	1
Number of terminals	-	-	-	28	-	28	28	28	28
Maximum operating temperature	-	-	-	85 °C	-	85 °C	85 °C	85 °C	85 °C
Package body material	-	-	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	-	QCCJ	-	QCCJ	QCCJ	QCCJ	QCCJ
Encapsulate equivalent code	-	-	-	LDCC28,.5SQ	-	LDCC28,.5SQ	LDCC28,.5SQ	LDCC28,.5SQ	LDCC28,.5SQ
Package shape	-	-	-	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE
Package form	-	-	-	CHIP CARRIER	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
power supply	-	-	-	-5.2 V	-	-5.2 V	-5.2 V	-4.5 V	-4.5 V
Maximum supply current (ICC)	-	-	-	145 mA	-	145 mA	145 mA	167 mA	167 mA
propagation delay (tpd)	-	-	-	4.8 ns	-	4.8 ns	4.8 ns	4.8 ns	4.95 ns
Certification status	-	-	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	-	-	-	YES	-	YES	YES	YES	YES
technology	-	-	-	ECL	-	ECL	ECL	ECL	ECL
Temperature level	-	-	-	OTHER	-	OTHER	OTHER	OTHER	INDUSTRIAL
Terminal surface	-	-	-	Tin/Lead (Sn85Pb15)	-	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	-	-	-	J BEND	-	J BEND	J BEND	J BEND	J BEND
Terminal pitch	-	-	-	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	-	-	-	QUAD	-	QUAD	QUAD	QUAD	QUAD
Trigger type	-	-	-	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
minfmax	-	-	-	1800 MHz	-	1800 MHz	1800 MHz	1800 MHz	2200 MHz

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