W83627UHG
NCT6627UD
NUVOTON LPC I/O
Date: April 1
st
, 2010 Revision: 1.6
-I-
Publication Release Date: April 1, 2010
Revision 1.6
TABLE OF CONTENTS –
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES ................................................................................................................................. 3
BLOCK DIAGRAM ...................................................................................................................... 6
PIN LAYOUT............................................................................................................................... 7
PIN DESCRIPTION..................................................................................................................... 8
5.1
LPC Interface ........................................................................................................................ 9
5.2
FDC Interface........................................................................................................................ 9
5.3
Multi-Mode Parallel Port...................................................................................................... 11
5.4
Serial Port & Infrared Port Interface.................................................................................... 12
5.5
KBC Interface...................................................................................................................... 17
5.6
Hardware Monitor Interface ................................................................................................ 18
5.7
PECI Interface..................................................................................................................... 19
5.8
SST Interface ...................................................................................................................... 19
5.9
Advanced Configuration and Power Interface .................................................................... 19
5.10 General Purpose I/O Port ................................................................................................... 19
5.10.1
5.10.2
5.10.3
5.10.4
5.10.5
5.10.6
5.10.7
5.10.8
GPIO Power Source ..................................................................................................................19
GPIO-1 Interface .......................................................................................................................20
GPIO-2 Interface .......................................................................................................................20
GPIO-3 Interface .......................................................................................................................20
GPIO-4 Interface .......................................................................................................................20
GPIO-5 Interface .......................................................................................................................20
GPIO-6 Interface .......................................................................................................................21
WDTO# and SUSLED Pins .......................................................................................................21
5.11 POWER PINS ..................................................................................................................... 21
6.
CONFIGURATION REGISTER ACCESS PROTOCOL ........................................................... 22
6.1 Configuration Sequence............................................................................................................ 24
6.1.1
6.1.2
6.1.3
6.1.4
Enter the Extended Function Mode.............................................................................................24
Configure the Configuration Registers ........................................................................................25
Exit the Extended Function Mode ...............................................................................................25
Software Programming Example.................................................................................................25
7.
HARDWARE MONITOR ........................................................................................................... 27
7.1
General Description ............................................................................................................ 27
7.2
Access Interfaces................................................................................................................ 28
7.2.1
7.2.2
LPC Interface ..............................................................................................................................28
I
2
C Interface ................................................................................................................................30
Voltages Over 2.048 V or Less Than 0 V ....................................................................................33
Voltage Detection........................................................................................................................34
Temperature Sensing..................................................................................................................34
Command Summary ...................................................................................................................37
Combination Sensor Data Format...............................................................................................38
7.3
Analog Inputs ...................................................................................................................... 32
7.3.1
7.3.2
7.3.3
7.4
SST Command Summary ................................................................................................... 36
7.4.1
7.4.2
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Publication Release Date: April 1, 2010
Revision 1.6
7.5
7.6
PECI.................................................................................................................................... 39
Fan Speed Measurement and Control................................................................................ 42
7.6.1
7.6.2
7.6.3
Fan Speed Measurement............................................................................................................42
Fan Speed Control ......................................................................................................................43
SMART FAN
TM
Control ...............................................................................................................44
SMI# Interrupt Mode ...................................................................................................................52
OVT# Interrupt Mode ..................................................................................................................55
Caseopen Detection....................................................................................................................55
BEEP Alarm Function .................................................................................................................56
7.7
Interrupt Detection .............................................................................................................. 52
7.7.1
7.7.2
7.7.3
7.7.4
8.
HARDWARE MONITOR REGISTER SET................................................................................ 58
8.1
Address Port (Port x5h) ...................................................................................................... 58
8.2
Data Port (Port x6h) ............................................................................................................ 58
8.3
SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) ....... 59
8.4
SYSFANOUT Output Value Select Register - Index 01h (Bank 0)..................................... 59
8.5
CPUFANOUT PWM Output Frequency Configuration Register - Index 02h (Bank 0) ....... 60
8.6
CPUFANOUT Output Value Select Register - Index 03h (Bank 0) .................................... 61
8.7
FAN Configuration Register I - Index 04h (Bank 0) ............................................................ 61
8.8
SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h
(Bank 0) ........................................................................................................................................... 62
8.9
CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register - Index 06h
(Bank 0) ........................................................................................................................................... 62
8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0) ........... 63
8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) ................................................... 63
8.12 CPUFANOUT Stop Value Register - Index 09h (Bank 0)................................................... 63
8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) ............................................. 64
8.14 CPUFANOUT Start-up Value Register - Index 0Bh (Bank 0)............................................. 64
8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0).................................................... 65
8.16 CPUFANOUT Stop Time Register - Index 0Dh (Bank 0) ................................................... 65
8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0).............................................. 65
8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0) .................................................. 66
8.19 Reserved Registers - Index 10h (Bank 0)........................................................................... 66
8.20 Reserved Registers - Index 11h (Bank 0)........................................................................... 66
8.21 FAN Configuration Register II - Index 12h (Bank 0) ........................................................... 66
8.22 Reserved Registers - Index 13h (Bank 0)........................................................................... 67
8.23 Reserved Registers - Index 14h (Bank 0)........................................................................... 67
8.24 Reserved Registers - Index 15h (Bank 0)........................................................................... 67
8.25 Reserved Registers - Index 16h (Bank 0)........................................................................... 67
8.26 Reserved Registers - Index 17h (Bank 0)........................................................................... 67
8.27 OVT# Configuration Register - Index 18h (Bank 0) ............................................................ 67
8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) ................................................................ 67
8.29 Value RAM
⎯
Index 20h ~ 3Fh (Bank 0) ........................................................................... 68
8.30 Configuration Register - Index 40h (Bank 0) ...................................................................... 69
8.31 Interrupt Status Register 1 - Index 41h (Bank 0) ................................................................ 70
Publication Release Date: April 1, 2010
Revision 1.6
-III-
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
8.62
8.63
8.64
8.65
8.66
8.67
8.68
8.69
8.70
8.71
8.72
8.73
8.74
8.75
Interrupt Status Register 2 - Index 42h (Bank 0) ................................................................ 70
SMI# Mask Register 1 - Index 43h (Bank 0)....................................................................... 71
SMI# Mask Register 2 - Index 44h (Bank 0)....................................................................... 71
Reserved Register - Index 45h (Bank 0) .......................................................................... 72
SMI# Mask Register 3 - Index 46h (Bank 0)....................................................................... 72
Fan Divisor Register I - Index 47h (Bank 0)........................................................................ 72
Serial Bus Address Register - Index 48h (Bank 0) ............................................................. 72
CPUFANOUT monitor Temperature source select register - Index 49h (Bank 0).............. 73
SYSFANOUT monitor Temperature source select register - Index 4Ah (Bank 0).............. 73
Fan Divisor Register II - Index 4Bh (Bank 0) ...................................................................... 74
SMI#/OVT# Control Register - Index 4Ch (Bank 0)............................................................ 75
FAN IN/OUT Control Register - Index 4Dh (Bank 0) .......................................................... 75
Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) ........................................ 77
Nuvoton Vendor ID Register - Index 4Fh (Bank 0)............................................................. 77
Reserved Register - Index 50h ~ 55h (Bank 0) .................................................................. 78
BEEP Control Register 1 - Index 56h (Bank 0)................................................................... 78
BEEP Control Register 2 - Index 57h (Bank 0)................................................................... 79
Chip ID - Index 58h (Bank 0) .............................................................................................. 79
Reserved Register - Index 59h (Bank 0) ............................................................................ 79
Reserved Register - Index 5Ah ~ 5Ch (Bank 0) ................................................................. 80
VBAT Monitor Control Register - Index 5Dh (Bank 0) ........................................................ 80
Critical Temperature enable register - Index 5Eh (Bank 0) ................................................ 80
Reserved Register - Index 5Fh (Bank 0) ............................................................................ 81
Reserved Registers - Index 60h (Bank 0)........................................................................... 81
Reserved Registers - Index 61h (Bank 0)........................................................................... 81
Reserved Registers - Index 62h (Bank 0)........................................................................... 81
Reserved Registers - Index 63h (Bank 0)........................................................................... 81
Reserved Registers - Index 64h (Bank 0)........................................................................... 81
Reserved Registers - Index 65h (Bank 0)........................................................................... 81
Reserved Registers - Index 66h (Bank 0)........................................................................... 82
CPUFANOUT Maximum Output Value Register - Index 67h (Bank 0)............................... 82
CPUFANOUT Output Step Value Register - Index 68h (Bank 0)....................................... 83
Reserved Registers - Index 69h (Bank 0)........................................................................... 83
Reserved Registers - Index 6Ah (Bank 0) .......................................................................... 83
SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0) ..................................... 83
CPUFANOUT Critical Temperature register - Index 6Ch (Bank 0) .................................... 83
Reserved Registers - Index 6Dh (Bank 0) .......................................................................... 83
Reserved Registers - Index 6Eh (Bank 0) .......................................................................... 84
CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1) ............................ 84
CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1) ............................. 84
CPUTIN Configuration Register - Index 52h (Bank 1)........................................................ 84
CPUTIN Hysteresis (High Byte) Register - Index 53h (Bank 1) ......................................... 85
CPUTIN Hysteresis (Low Byte) Register - Index 54h (Bank 1) .......................................... 85
CPUTIN Over-temperature (High Byte) Register - Index 55h (Bank1)............................... 85
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Publication Release Date: April 1, 2010
Revision 1.6
8.76 CPUTIN Over-temperature (Low Byte) Register - Index 56h (Bank 1)............................... 86
8.77 SYSTIN/CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 2) .............. 86
8.78 SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2) .............. 86
8.79 Reserved Registers – Index 52h (Bank 2).......................................................................... 87
8.80 Reserved Registers – Index 53h (Bank 2).......................................................................... 87
8.81 Reserved Registers – Index 54h (Bank 2).......................................................................... 87
8.82 Reserved Registers – Index 55h (Bank 2).......................................................................... 87
8.83 Reserved Registers – Index 56h (Bank 2).......................................................................... 87
8.84 Interrupt Status Register 3 – Index 50h (Bank 4) ............................................................... 87
8.85 SMI# Mask Register 4 – Index 51h (Bank 4) ...................................................................... 87
8.86 Reserved Register - Index 52h (Bank 4) ............................................................................ 88
8.87 BEEP Control Register 3 - Index 53h (Bank 4)................................................................... 88
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) .................................. 89
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4).................................. 89
8.90 Reserved Registers - Index 56h (Bank 4)........................................................................... 89
8.91 Reserved Register - Index 57h-58h (Bank 4) ..................................................................... 89
8.92 Real Time Hardware Status Register I - Index 59h (Bank 4) ............................................. 89
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4) ............................................ 90
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4) ........................................... 91
8.95 Reserved Register - Index 5Ch - 5Fh (Bank 4) .................................................................. 91
8.96 Value RAM 2
⎯
Index 50h-59h (Bank 5) ........................................................................... 91
8.97 Reserved Register - Index 50h - 57h (Bank 6) ................................................................... 92
9.
FLOPPY DISK CONTROLLER ................................................................................................. 93
9.1
FDC Functional Description ................................................................................................ 93
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
FIFO (Data) .................................................................................................................................93
Data Separator............................................................................................................................94
Write Precompensation ...............................................................................................................94
Perpendicular Recording Mode...................................................................................................94
FDC Core ....................................................................................................................................94
FDC Commands .........................................................................................................................95
Status Register A (SA Register) (Read base address + 0) .......................................................103
Status Register B (SB Register) (Read base address + 1) .......................................................104
Digital Output Register (DO Register) (Write base address + 2)...............................................105
Tape Drive Register (TD Register) (Read base address + 3) ...................................................106
Main Status Register (MS Register) (Read base address + 4) .................................................107
Data Rate Register (DR Register) (Write base address + 4).....................................................108
FIFO Register (R/W base address + 5).....................................................................................109
Digital Input Register (DI Register) (Read base address + 7) ...................................................112
Configuration Control Register (CC Register) (Write base address + 7) ...................................113
9.2
Register Descriptions........................................................................................................ 103
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
10.
UART PORT ........................................................................................................................... 115
10.1 Universal Asynchronous Receiver/Transmitter (UART A, B, C, D, E, F) ......................... 115
10.2 Register Address .............................................................................................................. 115
10.2.1
UART Control Register (UCR) (Read/Write)............................................................................115
-V-
Publication Release Date: April 1, 2010
Revision 1.6