8-/10-/12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452/AD5453
FEATURES
12 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8-bit
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 μA typical current consumption
Guaranteed monotonic
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REF
R
FB
AD5450/
AD5451/
AD5452/
AD5453
R
8-/10-/12-/14-BIT REF
R-2R DAC
I
OUT
1
DAC REGISTER
POWER-ON
RESET
INPUT LATCH
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GND
Figure 1.
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD5453
1
are CMOS 8-/10-/
12-/14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply, making
them suited to several applications, including battery-powered
applications.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. Upon power-up, the internal shift
register and latches are filled with 0s, and the DAC output is at
zero scale.
The applied external reference input voltage (V
REF
) determines
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(R
FB
) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages.
1
U.S. Patent Number 5,689,257.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
04587-001
SYNC
SCLK
SDIN
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
AD5450/AD5451/AD5452/AD5453
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 15
General Description ....................................................................... 16
DAC Section................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 18
Adding Gain................................................................................ 18
Divider or Programmable Gain Element................................ 19
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Serial Interface ............................................................................ 21
Microprocessor Interfacing....................................................... 21
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the DAC...................................................... 24
Power Supplies for the Evaluation Board................................ 24
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
3/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 4
Changes to Figure 27 and Figure 28............................................. 11
Change to Table 9 ........................................................................... 20
Changes to Table 12........................................................................ 26
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
7/05—Rev. 0 to Rev. A
Added AD5453 ...................................................................Universal
Changes to Specifications ................................................................ 4
Change to Figure 21 ....................................................................... 10
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD5450/AD5451/AD5452/AD5453
SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V, V
REF
= 10 V. Temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5450
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5451
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5452
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5453
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
Gain Error Temperature Coefficient
1
Output Leakage Current
REFERENCE INPUT
1
Reference Input Range
V
REF
Input Resistance
R
FB
Feedback Resistance
Input Capacitance
Zero-Scale Code
Full-Scale Code
DIGITAL INPUTS/OUTPUTS
1
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output High Voltage, V
OH
Output Low Voltage, V
OL
Input Leakage Current, I
IL
Input Capacitance
V
DD
− 1
V
DD
− 0.5
0.4
0.4
±1
±10
10
Min
Typ
Max
Unit
Conditions
8
±0.25
±0.5
±0.5
±0.25
10
±0.25
±0.5
±0.5
±0.25
12
±0.5
±1
±1
±0.5
14
±2
−1/+2
±4
±2.5
±2
±1
±10
±10
9
9
18
18
2.0
1.7
0.8
0.7
Bits
LSB
LSB
LSB
LSB
Bits
LSB
LSB
LSB
LSB
Bits
LSB
LSB
LSB
LSB
Bits
LSB
LSB
LSB
LSB
ppm FSR/°C
nA
nA
V
kΩ
kΩ
pF
pF
V
V
V
V
V
V
V
V
nA
nA
pF
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0x0000, T
A
= 25°C, I
OUT
1
Data = 0x0000, T
A
= −40°C to +125°C, I
OUT
1
7
7
11
11
22
22
Input resistance, TC = −50 ppm/°C
Input resistance, TC = −50 ppm/°C
V
DD
= 3.6 V to 5 V
V
DD
= 2.5 V to 3.6 V
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.5 V to 2.7 V
V
DD
= 4.5 V to 5 V, I
SOURCE
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SOURCE
= 200 μA
V
DD
= 4.5 V to 5 V, I
SINK
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SINK
= 200 μA
T
A
= 25°C
T
A
= −40°C to +125°C
Rev. B | Page 3 of 28
AD5450/AD5451/AD5452/AD5453
Parameter
DYNAMIC PERFORMANCE
1
Reference-Multiplying BW
Multiplying Feedthrough Error
Min
Typ
12
72
64
44
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
I
OUT
1
I
OUT
2
Digital Feedthrough
Analog THD
Digital THD
50 kHz f
OUT
20 kHz f
OUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz f
OUT
20 kHz f
OUT
SFDR Performance (Narrow Band)
50 kHz f
OUT
20 kHz f
OUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range
I
DD
Power Supply Sensitivity
1
1
Max
Unit
MHz
dB
dB
dB
Conditions
V
REF
= ±3.5 V, DAC loaded with all 1s
V
REF
= ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
V
REF
= 10 V, R
LOAD
= 100 Ω; DAC latch alternately
loaded with 0s and 1s
100
24
16
20
10
2
13
28
18
5
0.5
83
71
77
25
78
74
87
85
79
2.5
0.4
110
40
33
40
30
ns
ns
ns
ns
ns
nV-s
pF
pF
pF
pF
nV-s
dB
dB
dB
nV/√Hz
dB
dB
Interface delay time
Rise and fall times, V
REF
= 10 V, R
LOAD
= 100 Ω
1 LSB change around major carry, V
REF
= 0 V
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
V
REF
= 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, V
REF
= 3.5 V
@ 1 kHz
Clock = 1 MHz, V
REF
= 3.5 V
Clock = 1 MHz, V
REF
= 3.5 V
dB
dB
dB
5.5
10
0.6
0.001
V
μA
μA
%/%
f
1
= 20 kHz, f
2
= 25 kHz, clock = 1 MHz, V
REF
= 3.5 V
T
A
= −40°C to +125°C, logic inputs = 0 V or V
DD
T
A
= 25°C, logic inputs = 0 V or V
DD
∆V
DD
= ±5%
Guaranteed by design and characterization, not subject to production test.
Rev. B | Page 4 of 28
AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Update Rate
1
V
DD
= 2.5 V to 5.5 V
50
20
8
8
8
5
4.5
5
30
2.7
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
Guaranteed by design and characterization, not subject to production test.
t
1
SCLK
t
8
SYNC
t
2
t
3
t
7
t
4
t
6
04587-002
t
5
DIN
DB15
DB0
Figure 2. Timing Diagram
Rev. B | Page 5 of 28
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