Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
Symbol
R
qJC
R
qJA
T
L
Max
2.0
60
260
Unit
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted.)
Characteristic
OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current
(V
AK
= Rated V
DRM
or V
RRM
, Gate Open)
ON CHARACTERISTICS
Peak Forward On-State Voltage
(I
TM
= 24 A) (Note 3)
(I
TM
= 300 A, t
w
= 1 ms) (Note 4)
Gate Trigger Current (Continuous dc)
(V
D
= 12 V, R
L
= 100
W)
Gate Trigger Voltage (Continuous dc)
(V
D
= 12 V, R
L
= 100
W)
Gate Non−Trigger Voltage
(V
D
= 12 Vdc, R
L
= 100
W,
T
J
= 125°C)
Holding Current
(V
D
= 12 V, Initiating Current = 200 mA, Gate Open)
Latching Current
(V
D
= 12 Vdc, I
G
= 150 mA)
Gate Controlled Turn-On Time (Note 5)
(V
D
= Rated V
DRM
, I
G
= 150 mA)
(I
TM
= 24 A Peak)
DYNAMIC CHARACTERISTICS
Critical Rate-of-Rise of Off-State Voltage
(V
D
= Rated V
DRM
, Gate Open, Exponential Waveform, T
J
= 125°C)
Critical Rate-of-Rise of On-State Current
I
G
= 150 mA
T
J
= 125°C
dv/dt
di/dt
10
−
−
−
−
75
V/ms
A/ms
V
TM
−
−
I
GT
V
GT
V
GD
I
H
I
L
t
gt
2.0
−
0.2
3.0
−
−
−
6.0
7.0
0.65
0.40
15
−
1.0
2.2
−
30
1.5
−
50
60
−
mA
V
V
mA
mA
ms
V
I
DRM
, I
RRM
T
J
= 25°C
T
J
= 125°C
−
−
−
−
10
2.0
mA
mA
Symbol
Min
Typ
Max
Unit
3. Pulse duration
p
300
ms,
duty cycle
p
2%.
4. Ratings apply for t
w
= 1 ms. See Figure 1 for I
TM
capability for various durations of an exponentially decaying current waveform. t
w
is defined
as 5 time constants of an exponentially decaying current pulse.
5. The gate controlled turn-on time in a crowbar circuit will be influenced by the circuit inductance.
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2
MCR68−2
Voltage Current Characteristic of SCR
+ Current
Anode +
V
TM
on state
I
RRM
at V
RRM
I
H
Symbol
V
DRM
I
DRM
V
RRM
I
RRM
V
TM
I
H
Parameter
Peak Repetitive Off State Forward Voltage
Peak Forward Blocking Current
Peak Repetitive Off State Reverse Voltage
Peak Reverse Blocking Current
Peak On State Voltage
Holding Current
Reverse Blocking Region
(off state)
Reverse Avalanche Region
Anode −
+ Voltage
I
DRM
at V
DRM
Forward Blocking Region
(off state)
I TM , PEAK DISCHARGE CURRENT (AMPS)
NORMALIZED PEAK CURRENT
1000
300
200
100
50
20
0.5
I
TM
t
w
t
w
= 5 time constants
1.0
2.0
5.0
10
20
50
1.0
0.8
0.6
0.4
0.2
0
25
50
75
100
125
T
C
, CASE TEMPERATURE (°C)
t
w
, PULSE CURRENT DURATION (ms)
Figure 1. Peak Capacitor Discharge Current
Figure 2. Peak Capacitor Discharge Current
Derating
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
TC , MAXIMUM CASE TEMPERATURE (
°
C)
125
120
115
110
dc
20
18
14
Half Wave
dc
105
100
95
90
85
80
75
1.0
2.0
5.0
8.0
10
I
T(AV)
, AVERAGE ON-STATE CURRENT (AMPS)
Half Wave
10
8.0
4.0
2.0
1.0
4.0 5.0
8.0
I
T(AV)
, AVERAGE ON-STATE CURRENT (AMPS)
2.0
10
T
J
= 125°C
Figure 3. Current Derating
Figure 4. Maximum Power Dissipation
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3
MCR68−2
r(t), TRANSIENT THERMAL RESISTANCE(NORMALIZED)
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.1
0.2
0.3
0.5
1
2
3
5
10
20
30
50
100
200 300
500
1k
2k 3k
5k
10 k
Z
qJC(t)
= R
qJC
•
r(t)
t, TIME (ms)
Figure 5. Thermal Response
NORMALIZED GATE TRIGGER CURRENT
10
NORMALIZED GATE TRIGGER VOLTAGE
5.0
3.0
2.0
1.0
0.5
0.3
0.2
−60
−40
−20
0
20
40
60
80 100
T
J
, JUNCTION TEMPERATURE (°C)
120
140
1.4
V
D
= 12 Volts
R
L
= 100
W
V
D
= 12 Volts
R
L
= 100
W
1.2
1.0
0.8
0.5
−60
−40
−20
0
20
40
60
80
100
120
140
T
J
, JUNCTION TEMPERATURE (°C)
Figure 6. Gate Trigger Current
Figure 7. Gate Trigger Voltage
3.0
NORMALIZED HOLD CURRENT
2.0
V
D
= 12 Volts
I
TM
= 100 mA
1.0
0.8
0.5
0.3
−60
−40
−20
0
20
40
60
80
100
120
140
T
J
, JUNCTION TEMPERATURE (°C)
Figure 8. Holding Current
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4
MCR68−2
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−07
ISSUE AA
−T−
B
F
C
SEATING
PLANE
T
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.014
0.022
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−− 0.080
CATHODE
ANODE
GATE
ANODE
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.36
0.55
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
4
Q
1 2 3
A
U
K
H
Z
L
V
G
D
N
J
R
STYLE 3:
PIN 1.
2.
3.
4.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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