Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Data retention: 20 years at 85°C / 100 years at 25C
– Programming Lock for Self-Programming Flash Program & EEPROM Data Security
Peripheral Features
– 8/16-bit Timer/Counter with Prescaler
– 8/10-bit High Speed Timer/Counter with Separate Prescaler
• 3 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– 10-bit ADC
• 11 Single-Ended Channels
• 16 Differential ADC Channel Pairs
• 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Universal Serial Interface with Start Condition Detector
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
I/O and Packages
– 16 Programmable I/O Lines
– Available in 20-pin PDIP, 20-pin SOIC and 32-pad MLF
Operating Voltage:
– 1.8 – 5.5V for ATtiny261V/461V/861V
– 2.7 – 5.5V for ATtiny261/461/861
Speed Grade:
– ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode (1 MHz System Clock): 300 µA @ 1.8V
– Power-Down Mode: 0.1 µA at 1.8V
•
•
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny261/V*
ATtiny461/V
ATtiny861/V
Summary
*Mature
•
•
•
•
•
•
2588FS–AVR–06/2013
ATtiny261/461/861
1. Pin Configurations
Figure 1-1.
Pinout ATtiny261/461/861 and ATtiny261V/461V/861V
PDIP/SOIC
(MOSI/DI/SDA/OC1A/PCINT8) PB0
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
VCC
GND
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
AVCC
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
32
31
30
29
28
27
26
25
PB2 (SCK/USCK/SCL/OC1B/PCINT10)
PB1 (MISO/DO/OC1A/PCINT9)
PB0 (MOSI/DI/SDA/OC1A/PCINT8)
NC
NC
NC
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
NC
(OC1B/PCINT11) PB3
NC
VCC
GND
NC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
1
2
3
4
5
6
7
8
QFN/MLF
24
23
22
21
20
19
18
17
NC
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
NC
NC
AVCC
PA4 (ADC3/ICP0/PCINT4)
Note:
To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board.
NC
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
NC
(ADC6/AIN1/PCINT7) PA7
(ADC5/AIN0/PCINT6) PA6
(ADC4/AIN2/PCINT5) PA5
NC
9
10
11
12
13
14
15
16
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2588FS–AVR–06/2013
ATtiny261/461/861
1.1
1.1.1
Pin Descriptions
VCC
Supply voltage.
1.1.2
GND
Ground.
1.1.3
AVCC
Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC),
the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port
A. It should be externally connected to VCC, even if some peripherals such as the ADC are not
used. If the ADC is used AVCC should be connected to VCC through a low-pass filter.
1.1.4
AGND
Analog ground.
1.1.5
Port A (PA7:PA0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port A also serves the functions of various special features of the device, as listed on
page 63.
1.1.6
Port B (PB7:PB0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port B also serves the functions of various special features of the device, as listed on
page 66.
1.1.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in
Table 19-4 on page 190.
Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
2588FS–AVR–06/2013
ATtiny261/461/861
2. Overview
ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
GND
VCC
Watchdog
Timer
Watchdog
Oscillator
Power
Supervision
POR / BOD &
RESET
debugWIRE
PROGRAM
LOGIC
Oscillator
Circuits /
Clock
Generation
Flash
SRAM
CPU
EEPROM
AVCC
AGND
AREF
Timer/Counter0
DATABUS
Timer/Counter1
A/D Conv.
USI
Analog Comp.
Internal
Bandgap
3
11
PORT B (8)
PORT A (8)
RESET
XTAL[1..2]
PB[0..7]
PA[0..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
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2588FS–AVR–06/2013
ATtiny261/461/861
The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32
general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-bit high
speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-chan-
nel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software
selectable power saving modes. Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-
down mode saves the register contents, disabling all chip functions until the next Interrupt or
Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261/461/861 AVR is supported by a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation
kits.
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2588FS–AVR–06/2013
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