STM32L496ZGT6 datasheet, PDF - EEWORLD Datasheet

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STM32L496ZGT6: DescriptionIC MCU 32BIT 1MB FLASH 144LQFP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，280 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM32L496ZGT6 Overview

IC MCU 32BIT 1MB FLASH 144LQFP

STM32L496ZGT6 Parametric

Parameter Name	Attribute value
Brand Name	STMicroelectronics
Maker	STMicroelectronics
package instruction	LFQFP,
Reach Compliance Code	compliant
Factory Lead Time	14 weeks
Has ADC	YES
Address bus width	26
bit size	32
maximum clock frequency	48 MHz
DMA channel	YES
External data bus width	16
length	20 mm
Number of I/O lines	115
Number of terminals	144
PWM channel	YES
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
speed	80 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	1.8 V
Nominal supply voltage	3 V
surface mount	YES
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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STM32L496xx

Ultra-low-power Arm

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS

Datasheet

production data

Features

•

Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/125 °C temperature range

– 320 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 25 nA Shutdown mode (5 wakeup pins)

– 108 nA Standby mode (5 wakeup pins)

– 426 nA Standby mode with RTC

– 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with

RTC

– 91 µA/MHz run mode (LDO Mode)

– 37

μA/MHz

run mode (@3.3 V SMPS

Mode)

– Batch acquisition mode (BAM)

– 5 µs wakeup from Stop mode

– Brown out reset (BOR) in all modes except

shutdown

– Interconnect matrix

•

Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100 DMIPS and DSP instructions

•

Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 Coremark

(3.42 Coremark/MHz @

80 MHz)

•

Energy benchmark

– 279 ULPMark™ CP score

– 80.2 ULPMark™ PP score

•

16 x timers: 2 x 16-bit advanced motor-control,

2 x 32-bit and 5 x 16-bit general purpose,

2 x 16-bit basic, 2 x low-power 16-bit timers

(available in Stop mode), 2 x watchdogs,

SysTick timer

•

RTC with HW calendar, alarms and calibration

LQFP144 (20 × 20)

LQFP100 (14 x 14)

LQFP64 (10 x 10)

UFBGA169 (7 x 7)

UFBGA132 (7 × 7)

WLCSP100

•

Up to 136 fast I/Os, most 5 V-tolerant, up to 14

I/Os with independent supply down to 1.08 V

•

Dedicated Chrom-ART Accelerator™ for

enhanced graphic content creation (DMA2D)

•

8- to 14-bit camera interface up to 32 MHz

(black&white) or 10 MHz (color)

•

Memories

– Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– 320 KB of SRAM including 64 KB with

hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM,

NOR and NAND memories

– Dual-flash Quad SPI memory interface

•

Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25% accuracy)

– Internal 48 MHz with clock recovery

– 3 PLLs for system clock, USB, audio, ADC

•

LCD 8 × 40 or 4 × 44 with step-up converter

•

Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

•

4 x digital filters for sigma delta modulator

•

Rich analog peripherals (independent supply)

– 3 × 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

September 2018

This is information on a product in full production.

DS11585 Rev 10

1/280

www.st.com

STM32L496xx

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

Arm

Cortex

-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 22

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.1

3.10.2

3.10.3

3.10.4

3.10.5

3.10.6

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.11

3.12

3.13

3.14

3.15

3.16

Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.16.1

3.16.2

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41

Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 41

3.17

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.17.1

3.17.2

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DS11585 Rev 10

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Contents

3.17.3

STM32L496xx

VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.18

3.19

3.20

3.21

3.22

3.23

3.24

3.25

3.26

3.27

Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 46

Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.27.1

3.27.2

3.27.3

3.27.4

3.27.5

3.27.6

3.27.7

3.27.8

Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 50

Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

3.36

3.37

3.38

3.39

3.40

3.41

Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52

Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Universal synchronous/asynchronous receiver transmitter (USART) . . . 54

Low-power universal asynchronous receiver transmitter (LPUART) . . . . 55

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 57

Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 58

Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 58

Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 59

Dual-flash Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . 60

Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4/280

DS11585 Rev 10

STM32L496xx

3.41.1

3.41.2

Contents

Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 61

Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

6.3.10

6.3.11

6.3.12

6.3.13

6.3.14

6.3.15

6.3.16

6.3.17

6.3.18

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 128

Embedded reset and power control block characteristics . . . . . . . . . . 128

Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 166

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Extended interrupt and event controller input (EXTI) characteristics . . 185

Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 186

DS11585 Rev 10

5/280

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