DS1845B-010+T&R; datasheet, PDF

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DS1845B-010+T&R;: DescriptionIC POT/MEM DUAL NV 10K 16-BGA; Categorysemiconductor Analog mixed-signal IC; File Size194KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS1845B-010+T&R; Overview

IC POT/MEM DUAL NV 10K 16-BGA

DS1845B-010+T&R; Parametric

Parameter Name	Attribute value
cone	Linear
Configuration	Potentiometer
Number of circuits	2
Number of taps	100，256
Resistance (ohms)	10k
interface	I²C
memory type	non-volatile
Voltage - Power	2.7 V ~ 5.5 V
characteristic	Optional address
Tolerance	±20%
Temperature coefficient (typ.)	750 ppm/°C
Resistance - Vernier (Ohms) (Typical)	500
Operating temperature	-40°C ~ 85°C
Package/casing	16-LBGA，CSPBGA
Supplier device packaging	16-CSBGA（4x4）

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DS1845

Dual NV Potentiometer

and Memory

www.maxim-ic.com

FEATURES

Two linear taper potentiometers

DS1845-010 one 10k, 100 position &

one 10k, 256 position

DS1845-050 one 10k, 100 position &

one 50k, 256 postition

DS1845-100 one 10k, 100 position &

one 100k, 256 position

256 bytes of EEPROM memory

Access to data and potentiometer control via

an I

C compatible 2-wire interface

External Write Enable pin to protect data and

potentiometer settings

Nonvolatile wiper storage

Operates from 3V or 5V supplies

Packaging: Flip Chip Package, 16-ball

CSBGA, 14-pin TSSOP

Industrial operating temperature: -40ºC to

+85ºC

SDA

SCL

GND

Vcc

14-Pin TSSOP (173 mil)

Top View

16-Ball CSBGA (4mm x 4mm)

14-Pin Flip Chip (100-mil x 100-mil) (Not

Shown)

DESCRIPTION

The DS1845 Dual NV Potentiometer and Memory consists of one 100-position linear taper

potentiometer, one 256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire

interface. The device provides an ideal method for setting bias voltages and currents in control

applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration

or calibration data for a specific system or device as well as provide control of the potentiometer wiper

settings. Any type of user information may reside in the first 248 bytes of this memory. The next two

addresses of EEPROM memory are for potentiometer settings. Access to this EEPROM is via an

industry standard 2-wire bus. The wiper position of the DS1845, as well as EEPROM data, can be

hardware write-protected using the Write Protect (WP) input pin. Up to eight DS1845s can be installed

on a single 2-wire bus. Access to an individual device is achieved by using a device address that is

determined by the logic levels of address pins A0 though A2. Additionally, the DS1845 will operate

from 3 volt or 5 volt supplies. Three package options are available: Flip Chip Package, 16-ball CSBGA

and 14-pin TSSOP.

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011006

DS1845

2-Wire Interface Reset:

After any interruption in protocol, power loss, or system reset, the following

steps reset the DS1845.

1. Clock up to nine cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition while SDA is high.

Device Addressing:

The DS1845 must receive an 8-bit device address word following a start condition

to enable a specific device for a read or write operation. The address word is clocked into the DS1845

MSB to LSB. The address word consists of Ah (1010) followed by A2, A1, and A0 then the R/W

(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write

operation is initiated. For a device to become active, the values of A2, A1 and A0 must be the same as

the hard-wired address pins on the DS1845. Upon a match of written and hard-wired addresses, the

DS1845 will output a zero for one clock cycle as an acknowledge. If the address does not match the

DS1845 returns to a low-power mode.

Write Operations:

After receiving a matching address byte with the R/W bit set low, the device goes

into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the

device to define the address where the data is to be written. After the reception of this byte, the DS1845

will transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then

transmit an 8-bit data word to be written into this address. The DS1845 will again transmit a zero for one

clock cycle to acknowledge the receipt of the data. At this point the master must terminate the write

operation with a stop condition. The DS1845 then enters an internally timed write process t

to the

EEPROM memory. All inputs are disabled during this byte write cycle.

The DS1845 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,

but the master does not send a stop condition after the 1

byte. Instead, after the slave acknowledges

receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.

The master must terminate the write cycle with a stop condition or the data clocked into the DS1845 will

not be latched into permanent memory.

Acknowledge Polling:

Once the internally-timed write has started and the DS1845 inputs are disabled,

acknowledge polling can be initiated. The process involves transmitting a start condition followed by the

device address. The R/W bit signifies the type of operation that is desired. The read or write sequence

will only be allowed to proceed if the internal write cycle has completed and the DS1845 responds with a

zero.

Read Operations:

After receiving a matching address byte with the R/W bit set high, the device goes

into the read mode of operation. There are three read operations: current address read, random read and

sequential address read.

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DS1845

CURRENT ADDRESS READ

The DS1845 has an internal address register that maintains the address used during the last read or write

operation, incremented by one. This data is maintained as long as V

is valid. If the most recent

address was the last byte in memory, then the register resets to the first address. This address stays valid

between operations as long as power is available.

Once the device address is clocked in and acknowledged by the DS1845 with the R/W bit set to high, the

current address data word is clocked out. The master does not respond with a zero, but does generate a

stop condition afterwards.

RANDOM READ

A random read requires a dummy byte write sequence to load in the data word address. Once the device

and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must

generate another start condition. The master now initiates a current address read by sending the device

address with the read/write bit set high. The DS1845 will acknowledge the device address and serially

clocks out the data byte.

SEQUENTIAL ADDRESS READ

Sequential reads are initiated by either a current address read or a random address read. After the master

receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives

this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.

After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a stop condition. The master does

not respond with a zero.

For a more detailed description of 2-wire theory of operation, refer to the following section.

2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bi-directional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as

a receiver. The device that controls the message is called a “master.” The devices that are controlled by

the master are “slaves.” The bus must be controlled by a master device that generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as

a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for

the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is

provided in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy:

Both data and clock lines remain HIGH.

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