MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and
MFRC631
plus
Rev. 4.5 — 12 September 2018
227445
Product data sheet
COMPANY PUBLIC
1
General description
MFRC631, the cost efficient NFC frontend for payment.
The MFRC631 multi-protocol NFC frontend IC supports the following operating modes:
•
Read/write mode supporting ISO/IEC 14443 type A and MIFARE Classic
communication mode
•
Read/write mode supporting ISO/IEC 14443B
The MFRC631’s internal transmitter is able to drive a reader/writer antenna designed
to communicate with ISO/IEC 14443A and MIFARE Classic IC-based cards and
transponders without additional active circuitry. The digital module manages the
complete ISO/IEC 14443A framing and error detection functionality (parity and CRC).
The MFRC631 supports MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB
memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire
products. The MFRC631 supports higher transfer speeds of the MIFARE product family
up to 848 kbit/s in both directions.
The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer
communication scheme except anticollision. The anticollision needs to be implemented in
the firmware of the host controller as well as in the upper layers.
The following host interfaces are supported:
•
Serial Peripheral Interface (SPI)
•
Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
2
•
I C-bus interface (two versions are implemented: I2C and I2CL)
The MFRC631 supports the connection of a secure access module (SAM). A dedicated
2
separate I C interface is implemented for a connection of the SAM. The SAM can be
used for high secure key storage and acts as a very performant crypto coprocessor. A
dedicated SAM is available for connection to the MFRC631.
In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card.
NXP Semiconductors
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631
plus
MFRC631
2
Features and benefits
•
Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property
licensing rights
•
High-performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
•
Supports ISO/IEC 14443 type A, MIFARE Classic and ISO/IEC 14443 B modes
•
Supports MIFARE Classic product encryption by hardware in read/write mode
Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory,
MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and
MIFARE Plus ICs.
•
Low-power card detection
•
Compliance to "EMV contactless protocol specification V2.3.1" on RF level can be
achieved
•
Antenna connection with minimum number of external components
•
Supported host interfaces:
–
SPI up to 10 Mbit/s
2
–
I C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
–
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply
2
•
Separate I C-bus interface for connection of a secure access module (SAM)
•
FIFO buffer with size of 512 byte for highest transaction performance
•
Flexible and efficient power saving modes including hard power down, standby and
low-power card detection
•
Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal
•
3 V to 5.5 V power supply (MFRC63102)
2.5 V to 5.5 V power supply (MFRC63103)
•
Up to 8 free programmable input/output pins
•
Typical operating distance in read/write mode for communication to a ISO/IEC 14443
type A and MIFARE Classic card up to 12 cm, depending on the antenna size and
tuning
The version CLRC63103 offers a more flexible configuration for Low-Power Card
detection compared to the CLRC63102 with the new register LPCD_OPTIONS. In
addition, the CLRC63103 offers new additional settings for the Load Protocol which fit
very well to smaller antennas. The CLRC63103 is therefore the recommended version
for new designs.
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 12 September 2018
227445
2 / 149
NXP Semiconductors
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631
plus
MFRC631
3
Quick reference data
Parameter
supply voltage
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
TVDD supply current
operating ambient temperature
storage temperature
no supply voltage applied
PDOWN pin pulled HIGH
[2]
[1]
Table 1. Quick reference data MFRC63102HN
Symbol
V
DD
V
DD(PVDD)
V
DD(TVDD)
I
pd
I
DD
I
DD(TVDD)
T
amb
T
stg
[1]
[2]
Conditions
Min
3.0
3.0
3.0
-
-
-
-25
-55
Typ
5.0
5.0
5.0
8
17
100
+25
+25
Max
5.5
V
DD
5.5
40
20
250
+85
+125
Unit
V
V
V
nA
mA
mA
°C
°C
VDD(PVDD) must always be the same or lower voltage than VDD.
I
pd
is the sum of all supply currents
Table 2. Quick reference data MFRC63103HN
Symbol
V
DD
V
DD(PVDD)
V
DD(TVDD)
I
pd
I
DD
I
DD(TVDD)
T
amb
T
stg
[1]
[2]
Parameter
supply voltage
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
TVDD supply current
Conditions
[1]
Min
2.5
2.5
2.5
-
-
-
Typ
5.0
5.0
5.0
8
17
180
-
+25
+25
Max
5.5
V
DD
5.5
40
20
350
500
+105
+125
Unit
V
V
V
nA
mA
mA
mA
°C
°C
PDOWN pin pulled HIGH
[2]
absolute limiting value
operating ambient temperature device mounted on PCB which
allows sufficient heat dissipation
storage temperature
no supply voltage applied
-
-40
-55
VDD(PVDD) must always be the same or lower voltage than VDD.
I
pd
is the sum of all supply currents
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 12 September 2018
227445
3 / 149
NXP Semiconductors
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631
plus
MFRC631
4
Ordering information
Package
Name
Description
plastic thermal enhanced very thin quad flat package; no
leads; MSL1, 32 terminals + 1 central ground; body 5 × 5 ×
0.85 mm
plastic thermal enhanced very thin quad flat package; no
leads; MSL2, 32 terminals + 1 central ground; body 5 x 5 x
0.85 mm, wettable flanks
Version
SOT617-1
[1]
Table 3. Ordering information
Type number
MFRC63102HN/TRAYBM
MFRC63102HN/T/R
[2]
[3]
HVQFN32
MFRC63103HN/TRAYB
MFRC63103HN/T/R
[1]
[2]
[3]
[2]
SOT617-1
Delivered in five trays; MOQ: 5x 490 pcs
Delivered on reel with 6000 pieces; MOQ: 6000 pcs
Delivered in one tray, MOQ (Minimum order quantity) : 490 pcs
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 12 September 2018
227445
4 / 149
NXP Semiconductors
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631
plus
MFRC631
5
Block diagram
The analog interface handles the modulation and demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functionality.
REGISTER BANK
ANTENNA
ANALOG
INTERFACE
CONTACTLESS
UART
FIFO
BUFFER
SERIAL UART
SPI
I
2
C-BUS
HOST
001aaj627
Figure 1. Simplified block diagram of the MFRC631
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 12 September 2018
227445
5 / 149
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