74HC160
Presettable synchronous BCD decade counter;
asynchronous reset
Rev. 3 — 27 September 2016
Product data sheet
1. General description
The 74HC160 is a synchronous presettable decade counter with an internal look-ahead
carry. Synchronous operation is provided by having all flip-flops clocked simultaneously
on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may
be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting
action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on
the positive-going edge of the clock. Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW
regardless of the levels at input pins CP, PE, CET and CEP (thus providing an
asynchronous clear function). The look-ahead carry simplifies serial cascading of the
counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to
enable the terminal count output (TC). The TC output thus enabled will produce a HIGH
output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be
used to enable the next cascaded stage. The maximum clock frequency for the cascaded
counters is determined by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
1
f
max
=
---------------------------------------------------------------------------------------
-
t
P
max
CPtoTC
+
t
SU
CEPtoCP
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC160: CMOS level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Asynchronous reset
Positive-edge triggered clock
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC160D
74HC160DB
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC160
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 27 September 2016
2 of 19
Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration SSOP16
5.2 Pin description
Table 2.
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
V
CC
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC160
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 27 September 2016
4 of 19
Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
Reset (clear)
Parallel load
Count
Hold (do nothing)
L
H
H
H
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q
n
= lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
= LOW-to-HIGH clock transition.
[2]
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH);
Operating mode
Outputs
CP
X
X
X
CEP
X
X
X
h
I
X
CET
X
X
X
h
X
I
PE
X
I
I
h
h
h
Dn
X
I
h
X
X
X
Qn
L
L
H
count
q
n
q
n
TC
L
L
[2]
[2]
[2]
L
Fig 7.
State diagram
74HC160
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 27 September 2016
5 of 19
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