A product Line of
Diodes Incorporated
PI3WVR31212A
DP/HDMI 1:2 De-multiplexer switches
Features
ÎÎ
DP/HDMI 1:2 De-multiplexer switch with 4 high speed
Description
PI3WVR31212A has one passive output port1, one active (DP to
HDMI) output port2. Passive output supports DP1.2 at 5.4Gbps
in I2C mode. Active port2 supports HDMI1.4b at 3.4Gbps.All
two output ports support auto port priority selection. Input port
accepts DP1.2 and DP++ signals associated with output ports as
described above.
differential channel and AUX/DDC, HPD and CAB_DET
signal channels
ÎÎ
One passive output ports for DP1.2 at 5.4Gbps
ÎÎ
One active output port with integrated DP to HDMI re-
driver (level shifter) supports HDMI 1.4 at 3.4Gbps
ÎÎ
Pin control mode supports auto port priority selection
ÎÎ
Pin control mode supports port2 with DDC bi-direction
buffer switch only
Application
ÎÎ
Notebook and dongle
ÎÎ
I2C control mode supports auto port priority selection
ÎÎ
I2C control mode supports port2 with 8 levels equalization
and 5 levels pre-emphasis
Pin Configuration: TQFN-60
AUXN
AUXP
SCL2
SDA2
GND
GND
NC
AUX1P/SCL1
AUX1N/SDA1
CAB_1
60 59 58 57 56 55 54 53 52 51
ÎÎ
I2C control mode supports port2 with either DDC bi-
direction buffer switch or DDC passive switch
ÎÎ
Very low operating power when passive port1 is selected
ÎÎ
3.3V power supply
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2KV HBM ESD protection for all I/O pins
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Support Type 2 cable ID register
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Packaging:
60 pin TQFN package (5x9mm, 0.4mm pitch)
OEB
SCL
SDA
VDD
HPD_SRC
CAB_SRC
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
SDA_CTL/PRI_SEL
SCL_CTL/EQ
I2C_A1/PRE_EMP
I2C_A2/ROUT_SEL
HPD2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Center Pad
TQFN-60
5x9 mm
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VDD
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
GND
NC
NC
NC
GND
NC
NC
GND
CEXT
HPD1
MS
21 22 23 24 25 26 27 28 29 30
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CLKN2
CLKP2
VDD
D0N2
D0P2
D1N2
D1P2
VDD
D2N2
D2P2
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03/28/17
A product Line of
Diodes Incorporated
PI3WVR31212A
Block Diagram
CEXT
CAB_SRC HPD_SRC
120K
HPD1
HPD2
CAB_1
VDD
LDO
120K
100K
pull High
AUXP
AUXN
SDA
SCL
Cable ID
AUX1P/SCL1
AUX1N/SDA1
SDA2
SCL2
D[0:3]P1
D[0:3]N1
D[0:3]P
D[0:3]N
R
T
0//VDD
VDD
R
T
R
OUT
R
OUT
D[0:3]P2
D[0:3]N2
Port select
OEB
MS
PRI_SEL
EQ
PRE_EMP
ROUT_SEL
R
pd
GND
R
pd
Control & Status
Register
I2C
Controller
SDA_CTL
SCL_CTL
(share pins)
I2C_A1, A2
(share pins)
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A product Line of
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PI3WVR31212A
Pin Description
Pin#
7
9
11
13
8
10
12
14
49
47
45
43
48
46
44
42
25
27
30
22
24
26
29
21
52
53
57
58
60
59
3
2
32
19
5
Pin Name
D0P
D1P
D2P
D3P
D0N
D1N
D2N
D3N
D0P1
D1P1
D2P1
D3P1
D0N1
D1N1
D2N1
D3N1
D0P2
D1P2
D2P2
CLKP2
D0N2
D1N2
D2N2
CLKN2
AUX1N/SDA1
AUX1P/SCL1
SDA2
SCL2
AUXN
AUXP
SDA
SCL
HPD1
HPD2
HPD_SRC
Signal Type Description
IO
4 differential pair input (DP)
IO
4 differential pair output (DP) for port 1
IO
4 differential pair output (HDMI) for port 2
IO
AUX (DP) or DDC (HDMI) to two ports
IO
IO
I
I
O
AUX to DP-source
DDC to DP-source
HPD1-2 for port1-2;
HPD_SRC to DP-source.
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03/28/17
A product Line of
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PI3WVR31212A
Pin#
51
6
1
15
16
17
Pin Name
CAB_1
CAB_SRC
OEB
SDA_CTL/PRI_SE
SCL_CTL/EQ
I2C_A1/PRE_EMP
Signal Type Description
CAB_1: CAB_DET to port1
IO
I
I
IO
I
CAB_SRC: CAB_DET to DP-source
No CAB_DET for HDMI port2
OEB=0, device active; OEB=1, device shut down
MS=0, PRI_SEL selects priority in pin control mode;
MS=1, SDA_CTL as SDA in I2C control mode
MS=0, EQ selects equalization in pin control mode;
MS=1, SCL_CTL as SCL in I2C control mode
MS=0, PRE_EMP selects Pre-emphasis in pin control mode;
MS=1, I2C_A1 as I2C address A1 in I2C control mode
MS=0, ROUT_SEL selects source termination in pin control
mode;
MS=1, I2C_A2 as I2C address A2 in I2C control mode
Mode Select:
18
I2C_A2/ROUT_SEL
I
31
33
4, 23, 28, 50
20, 34, 37, 41, 55, 56,
Center Pad
35, 36, 38, 39, 40, 54
MS
CEXT
VDD
GND
NC
I
O
Power
Ground
NC
MS=0 for pin control mode
MS=1 for I2C control mode
Internal LDO bypass capacitance, 4.7uf to GND
3.3V VDD
Bottom GND EPAD
Not Connected
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03/28/17
A product Line of
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PI3WVR31212A
Pin mapping for dual mode DP source DEMUX to DP output
DP mode
ML_lane
ML_lane
ML_lane
ML_lane
ML_lane
ML_lane
ML_lane
ML_lane
HDMI/DVI mode WVR31212A input pins WVR31212A port1 output WVR31212A port2 output
TX2+
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
D2P2
D2N2
D1P2
D1N2
D0P2
D0N2
CLKP2
CLKN2
Function Description
The MS pin selects I2C or pin control mode.
Pin control mode has only automatic port selection. I2C control mode has automatic port selection.
In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high detected,
the PRI_SEL pin (priority select) will determine the priority of the 2 ports. See priority selection table
When PRI_SEL=low or High, the port-priority will be port1-port2 from high to low; when PRI_SEL=M (open as not connected), the
port priority will be port2-por1 from high to low.
When port 1 is selected and CAB_1 is low as in DP mode, the AUX/DDC channels will work as AUX channels. AUXP shall have
100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data rate of AUX channels will be
>720Mbps.The internal DDC switch will be off.
When port 1 is selected and CAB_1 is high when DP to HDMI adapter plugged, the AUX/DDC channels will work as DDC channels.
The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate 5V input and voltage of
DDC to source will be limited about 3.3V or below.
When port 1 is selected (passive ports), port2 with HDMI re-driver will shut down.
When port 2 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in pin
control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode.
When port 2 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source termina-
tion as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control.
When port 2 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive
DDC switch in I2C mode.
HPD1, HPD2 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs.
Squelch Mode
Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are
below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display.
Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold.
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Analog electronics
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