10G/25G High Speed
Ethernet Subsystem
v2.4
Product Guide
Vivado Design Suite
PG210 June 6, 2018
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance and Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Descriptions – MAC+PCS Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Descriptions – PCS Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Descriptions – 10G Ethernet MAC (64-bit) Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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15
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Chapter 3: Designing with the Subsystem
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LogiCORE Example Design Clocking and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for IEEE Standard 1588v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS-FEC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Datapath Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
802.1cm Preemption Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status/Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pause Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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150
160
164
165
171
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Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Design Hierarchy (GT in Example Design) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core xci Top Level Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duplex Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Runtime Switchable258. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shared Logic Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AXI4-Lite Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE Clause 108 (RS-FEC) Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
199
202
204
267
267
270
273
278
Chapter 6: Batch Mode Test Bench
Appendix A: Upgrading
Changes from v2.3 to v2.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changes from v2.3 (10/04/2017) to
v2.3 (12/20/2017) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changes from v2.2 to v2.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changes from v2.1 to v2.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changes from v2.0 to v2.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changes from v2.0 (10/05/2016) to v2.0 (11/30/2016) version. . . . . . . . . . . . . . . . . . . . . . . . . . .
Migrating from the Legacy XGEMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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284
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Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
306
308
308
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Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10G/25G High Speed Ethernet v2.4
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IP Facts
Introduction
The Xilinx® 10G/25G High Speed Ethernet
Subsystem implements the 25G Ethernet Media
Access Controller (MAC) with a Physical Coding
Sublayer (PCS) as specified by the 25G Ethernet
Consortium. MAC and physical coding
sublayer/physical medium attachment (PCS/
PMA) or PCS/PMA alone are available. Legacy
operation at 10 Gb/s is supported.
•
Optional fee-based Time Sensitive Networking
(TSN) feature designed to IEEE standard 802.1
CM
°
Supports interspersing express traffic
with low priority traffic
Supports frame preemption
Facts Table
Core Specifics
Zynq® UltraScale+™ MPSoC
Virtex® UltraScale+, Kintex® UltraScale+
Virtex UltraScale™, Kintex UltraScale
AXI4-Stream for Variants with MAC
XGMII or 25GMII for PCS-only variants
Performance and Resource Utilization web page
°
Features
•
Designed to the Ethernet requirements for 10/
25 Gb/s operation specified by IEEE 802.3
Clause 49, IEEE 802.3by, and the 25G Ethernet
Consortium
Includes complete Ethernet MAC and PCS/PMA
functions or standalone PCS/PMA for 25 Gb/s
operation
Includes complete Ethernet MAC and PCS/PMA
functions, standalone MAC or standalone PCS/
PMA for 10 Gb/s operation. Includes standalone
64-bit Ethernet MAC
Simple packet-oriented user interface
Comprehensive statistics gathering
Status signals for all major functional indicators
Delivered with a top-level wrapper including
functional transceiver wrapper, IP netlist,
sample test scripts, and Vivado® Design Suite
tools compile scripts
BASE-R PCS sublayer operating at 10.3125 Gb/s
or 25.78125 Gb/s
Supported
Device Family
(1)
Supported User
Interfaces
Resources
Provided with Core
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Encrypted register transfer level (RTL)
Verilog
Verilog
Xilinx Design Constraints (XDC)
Verilog
Linux
•
•
•
•
•
•
Tested Design Flows
(2)
Design Entry
Simulation
Synthesis
Vivado Design Suite
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synopsis or Vivado Synthesis
Support
Provided by Xilinx at the
Xilinx Support web page
•
•
•
•
•
•
•
Optional clause 74 BASE-KR FEC sublayer
Optional Auto-Negotiation
Optional clause 108 25G Reed-Solomon
Forward Error Correction (RS-FEC) sublayer
Custom Preamble mode
Optional IEEE 1588 1-step and 2-step
timestamping
Runtime switchable between 10G and 25G
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
Note:
To access the 25G specification, go to the
25G Ethernet Consortium
website.
10G/25G High Speed Ethernet v2.4
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Product Specification
Chapter 1
Overview
This document details the features of the 10G/25G Ethernet Subsystem as defined by the
25G Ethernet Consortium
[Ref 1].
PCS functionality is defined by
IEEE Standard 802.3, 2015,
Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R
[Ref 2].
For 25G
operation, clock frequencies are increased to provide a serial interface operating at
25.78125 Gb/s to leverage the latest high-speed serial transceivers. The low latency design
is optimized for UltraScale™ architecture devices.
Feature Summary
See
Table 1-1
for compatibility of options with the different variants of the LogiCORE™ IP
core.
25G Supported Features
•
•
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•
•
•
•
•
•
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Complete Ethernet MAC and PCS functions
Designed to Schedule 3 of the 25G Consortium
Statistics and diagnostics
66-bit serializer/deserializer (SerDes) interface using the Xilinx® GTY transceiver
operating with Asynchronous Gearbox enabled
Pause Processing including
IEEE std. 802.3
Annex 31D (Priority based Flow Control)
Low latency
Custom preamble and adjustable Inter Frame Gap
Configurable for operation at 10.3125 Gb/s (Clause 49)
Optional Clause 73 Auto-negotiation
Optional Clause 72.6.10 Link Training
Optional Clause 74 FEC – shortened cyclic code (2112, 2080)
Optional clause 108 25G Reed-Solomon Forward Error Correction (RS-FEC) sublayer
PCS only version with 25GMII Interface
10G/25G High Speed Ethernet v2.4
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